(SEM VI) THEORY EXAMINATION 2023-24 MICROPROCESSOR AND MICROCONTROLLER

MICROPROCESSOR AND MICROCONTROLLER – KEE602

Section-wise Important Questions & Ready Answers

SECTION A

(Attempt all – 2 marks each)

(a) Bus and Types of Buses in 8085

A bus is a set of parallel lines used to transfer data, address, and control signals between different components of a microprocessor system. The 8085 supports three buses: the address bus for memory addressing, the data bus for data transfer, and the control bus for timing and control operations.

(b) Uses of Accumulator Register

The accumulator is the primary register used for arithmetic and logical operations. It stores intermediate results and final outputs and is directly connected to the ALU, making it central to data processing.

(c) Flag Status for 52H + A8H (8085)

When 52H and A8H are added, the result is FAH. The sign flag is set since the MSB is 1. Zero flag is reset as the result is non-zero. Auxiliary carry flag is set due to carry from lower nibble. Parity flag is even, and carry flag remains reset.

(d) Flag Registers of 8086 Microprocessor

The 8086 has status flags such as carry, zero, sign, parity, auxiliary carry, overflow, and control flags including interrupt, direction, and trap flags. These flags reflect the result of operations and control processor behavior.

(e) Programming Techniques in 8085

Looping is used to execute a set of instructions repeatedly. Indexing accesses data using pointers or registers. Counting involves incrementing or decrementing values to track iterations or events.

(f) Control Signals Used for DMA Operation

DMA operation uses signals such as HOLD and HLDA to transfer control of buses from the microprocessor to the DMA controller.

(g) Ports in 8255 PPI

Port A of 8255 can be used in all modes of operation, while Port C is used for handshaking signals in mode 1 and mode 2 operations.

(h) TCON and TMOD SFR in 8051

TMOD selects timer modes and operation, while TCON controls timer start/stop and interrupt flags. These registers manage timer and external interrupt operations in 8051.

(i) PSW in 8051 Microcontroller

The Program Status Word (PSW) contains condition flags, register bank select bits, and parity flag. It reflects the status of arithmetic operations and controls register bank selection.

(j) Function of RS1 and RS0 Bits

RS1 and RS0 bits select one of the four register banks in the 8051 microcontroller, allowing efficient context switching during program execution.

SECTION B

(Attempt any three – 10 marks each)

1. Addressing Modes of 8085 Microprocessor

Addressing modes define how operands are accessed. Immediate addressing provides data directly, register addressing uses registers, direct addressing accesses memory locations, and implied addressing operates on predefined operands.

2. Addressing Modes of 8086 Microprocessor

8086 supports immediate, register, direct, register indirect, based, indexed, and based-indexed addressing modes. These modes provide flexibility in accessing data and memory.

3. 8255 Programmable Peripheral Interface (PPI)

The 8255 is a programmable I/O device with three ports. Mode 1 supports strobed input/output, and Mode 2 supports bidirectional data transfer with handshaking, enabling advanced peripheral communication.

4. Features and Internal Memory Organization of 8051

The 8051 has on-chip RAM, ROM, timers, serial communication, and I/O ports. Its internal data memory includes register banks, bit-addressable memory, and general-purpose RAM.

5. Assembly Language Programming, JUMP and CALL Instructions

Assembly language provides low-level control over hardware. JUMP instructions alter program flow, while CALL instructions invoke subroutines, improving program modularity.

SECTION C

Q3(a) Opcode Fetch Cycle and Timing Diagram

During opcode fetch, the microprocessor places the address on the bus, reads the instruction from memory, and decodes it. This cycle typically requires multiple T-states to complete.

Q3(b) Interrupts in 8086 Microprocessor

8086 supports hardware, software, and exception interrupts. These interrupts manage events like I/O requests and error handling.

Q4(a) Assembly Program to Find Highest Number

The program compares numbers sequentially using registers and conditional jumps to identify the highest value in a given data set.

Q4(b) Read Cycle Timing Diagram (8086 Minimum Mode)

In minimum mode, the microprocessor controls all bus operations. The read cycle includes address placement, memory enable, data transfer, and acknowledgment.

Q5(a) DMA Controller and 8237 Operation

The DMA controller transfers data directly between memory and I/O devices. The 8237 manages multiple channels and reduces CPU workload.

Q5(b) Modes of Operation of 8254

The 8254 timer operates in six modes including one-shot, rate generator, and square wave generator, enabling precise timing applications.

Q6(a) Harvard vs Von Neumann Architecture

Harvard architecture uses separate memory for data and instructions, offering faster access, while von Neumann uses a single memory, simplifying design.

Q6(b) Pin Diagram of 8051 Microcontroller

The 8051 pin diagram includes I/O ports, power pins, control signals, and oscillator pins, defining its interface with external components.

Q7(a) Difference Between PIC and ARM Processors

PIC processors are simple and cost-effective, used in small embedded systems. ARM processors offer high performance and are widely used in smartphones and advanced embedded systems.

Q7(b) Arithmetic and Logical Instructions of 8051

These instructions perform addition, subtraction, comparison, logical AND, OR, XOR, and bit manipulation, enabling efficient data processing.