(SEM VI) THEORY EXAMINATION 2017-18 INTEGRATED CIRCUIT TECHNOLOGY

Integrated Circuit Technology (NEC-603)

Complete Section-Wise Explanation – B.Tech Semester VI

Introduction to the Subject

Integrated Circuit Technology explains how electronic devices such as diodes, transistors, and MOSFETs are fabricated on a single silicon wafer to form an integrated circuit (IC). This subject bridges material science, semiconductor physics, and manufacturing technology, making it extremely important for electronics and VLSI students.

The paper mainly tests understanding of:

Silicon crystal growth                                  Oxidation and diffusion

Ion implantation                                          Lithography and etching

Epitaxy and metallization                            IC fabrication steps for Bipolar and MOS devices

Packaging and VLSI processes

The question paper is divided into three sections: A, B, and C, and all sections must be attempted as per instructions.

SECTION A – Fundamental Concepts (Short Answers)

Pattern:
Attempt all questions
10 questions × 2 marks = 20 marks

Nature of Section A

Section A checks whether your basic concepts are clear. Answers should be short, accurate, and technically correct. These questions often come directly from definitions and fabrication fundamentals.

Explanation of Section A Topics

Point Defects
Point defects are imperfections in a crystal lattice occurring at a single point, such as vacancies, interstitial atoms, or substitutional impurities. They significantly affect electrical properties of semiconductors.

Steps in Preparation of Silicon Wafers
Silicon wafers are prepared by crystal growth, slicing of ingots, lapping, polishing, cleaning, and inspection to obtain a defect-free surface suitable for IC fabrication.

SOI (Silicon on Insulator)
SOI is a technology where a thin silicon layer is formed on an insulating substrate, usually silicon dioxide, to reduce parasitic capacitance and improve device speed.

Oxidation Process and Properties of SiO₂
Oxidation is the process of growing a silicon dioxide layer on silicon by reacting it with oxygen or steam at high temperature. SiO₂ has excellent insulating properties and high thermal stability.

Isotropic and Anisotropic Etching
Isotropic etching removes material equally in all directions, while anisotropic etching removes material at different rates depending on crystal orientation.

Metallization
Metallization is the process of depositing metal layers (like aluminum or copper) to form electrical interconnections between devices in an IC.

Pseudo Homo-Epitaxy vs Hetero-Epitaxy
Pseudo homo-epitaxy involves growing doped silicon on silicon, while hetero-epitaxy involves growing a different semiconductor material on silicon.

Step Coverage Problem
Step coverage problem occurs when metal films do not uniformly cover steps and edges on the wafer surface, leading to poor interconnections.

Advantages of Ion Implantation
Ion implantation provides precise control of dopant concentration and depth, low temperature processing, and better uniformity compared to diffusion.

Difference Between Bipolar and MOS ICs
Bipolar ICs use both electrons and holes and offer high speed, while MOS ICs use majority carriers and provide low power consumption and high packing density.

SECTION B – Process Theory & Fabrication Concepts

Pattern:
Attempt any three questions
3 × 10 marks = 30 marks

Nature of Section B

This section requires descriptive answers in paragraph form, often supported by equations and diagrams. These questions test process understanding and fabrication logic.

Explanation of Important Section B Questions

Czochralski (CZ) Crystal Growth Process

The CZ process is used to grow single-crystal silicon ingots. A seed crystal is dipped into molten silicon and slowly pulled upward while rotating. The pull rate controls crystal diameter and dopant concentration. It is controlled by adjusting temperature and pulling speed.

Oxidation in IC Fabrication

Oxidation is essential for device isolation, surface passivation, and gate oxide formation. Oxide thickness depends on time and temperature. For short oxidation times, growth is linear, while for long times it follows a parabolic relationship as derived from oxidation kinetics.

Diffusion Process and Fick’s Law

Diffusion introduces dopants into silicon at high temperatures. Fick’s laws describe dopant movement due to concentration gradients. Diffusion depth is controlled by time, temperature, and diffusivity. Solutions include constant source and limited source diffusion.

Metallization and DC Sputtering

Metallization connects devices electrically. Common problems include hillock formation, poor adhesion, and electromigration.

In DC sputtering, ions strike a metal target, ejecting atoms that deposit on the wafer surface.

Fabrication of NPN Transistor and Comparison with NMOS

NPN transistor fabrication involves epitaxy, diffusion, oxidation, and metallization to form emitter, base, and collector regions. Compared to NMOS fabrication, bipolar processes are more complex and consume more power.

SECTION C – Advanced Processes & Numericals

Pattern:
Attempt any one part from each question
5 questions × 10 marks = 50 marks

This section carries the maximum weightage and requires clear explanations or accurate numerical solutions.

Question 3

Ion Implantation Process
Ion implantation accelerates dopant ions into silicon using an electric field. Implant depth depends on ion energy, while dose depends on ion current and time. Compared to diffusion, ion implantation offers better control and low-temperature processing.

CZ Method Numerical (Doping Concentration)
This numerical uses segregation coefficient to calculate required dopant concentration in molten silicon to achieve desired wafer doping.

Question 4

Epitaxy and Molecular Beam Epitaxy (MBE)
Epitaxy is the growth of a crystalline layer on a crystalline substrate. MBE uses molecular beams in ultra-high vacuum to achieve precise thickness and doping control. It offers better purity than VPE.

Film Deposition in IC Fabrication
Thin films such as oxide, nitride, polysilicon, and metal films are deposited using CVD, PVD, and epitaxial techniques.

Question 5

Self-Aligned Bipolar Structures and IIL
Self-aligned structures reduce parasitic capacitance and improve performance.
Integrated Injection Logic (IIL) is a low-power bipolar logic family used in early ICs.

Proximity Printing vs Projection Printing
Proximity printing places mask close to wafer, while projection printing uses optical systems. Projection printing offers higher resolution and better alignment.

Question 6

Wet Etching Kinetics and Photoresists
Wet etching involves chemical reactions that remove material. Gold is etched using specific chemical solutions like aqua regia.
Photoresists are light-sensitive materials used in lithography. Positive and negative PRs differ in exposure behavior.

Gaussian Diffusion Numerical
This numerical calculates diffusion time using Gaussian distribution, diffusivity, surface concentration, and junction depth.

Question 7

IC Packaging and DIP
Packaging protects ICs and provides electrical connections. DIP (Dual In-line Package) has two parallel rows of pins and is widely used in through-hole mounting.

Annealing and CVD
Annealing repairs crystal damage and activates dopants.
Chemical Vapor Deposition (CVD) deposits thin films through chemical reactions of gaseous precursors.