THEORY EXAMINATION (SEM–VI) 2016-17 ADVANCE DIGITAL DESIGN USING VERILOG

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ADVANCE DIGITAL DESIGN USING VERILOG (NEC024R)

Section-Wise Solved Answers

SECTION – A (Short Answer Questions)

(10 × 2 = 20 Marks)

(a) Advantages of HDLs

Hardware Description Languages (HDLs) allow designers to describe hardware at different abstraction levels. They support simulation, verification, easy modification, reusability, and synthesis into hardware, reducing design time and errors.

(b) Unary vs Ternary operator

Unary operator: Operates on a single operand (example: ~a, !a).

Ternary operator: Operates on three operands and is a conditional operator (condition ? expr1 : expr2).

(c) Difference between $monitor and $display

$display prints output once when executed, while $monitor continuously prints output whenever any monitored variable changes.

(d) Assignments in always vs initial

initial executes only once at the start of simulation, whereas always executes repeatedly whenever the sensitivity list conditions are met.

(e) Output of given Verilog code

always @(clk) begin a = 0; a <= 1; $display(a); end

The displayed value of a = 0, because the blocking assignment (a = 0) executes immediately, while the non-blocking assignment (a <= 1) updates later.

(f) Difference between == and ===

== checks logical equality and ignores X and Z.

=== checks case equality, including X and Z values.

(g) Difference between task and function

A function returns a value and cannot contain timing controls, while a task does not return a value and can include delays and event controls.

(h) Memory modeling components in Verilog

Memory is modeled using reg arrays, for example:

reg [7:0] mem [0:255];

(i) Feedback model vs Implicit model

Feedback model: Explicit feedback path is defined.

Implicit model: Feedback is inherent through procedural statements.

(j) Benefits of assertion verification

Assertions help detect design errors early, improve debugging efficiency, ensure design correctness, and enhance verification coverage.

SECTION – B (Long Answer Questions)

(Attempt any FIVE – 5 × 10 = 50 Marks)

2(a)(i) Verilog HDL and its capabilities

Verilog HDL is a hardware description language used to model digital systems. It supports behavioral, dataflow, and structural modeling. Its major capabilities include simulation, timing analysis, testbench creation, and synthesis into hardware.

2(a)(ii) Components of a Verilog module

A Verilog module consists of: Module declaration

Port list Declarations (wire, reg)

Continuous or procedural statements

Endmodule

2(b)(i) Data types in Verilog

Verilog data types include:

Net types: wire, tri Register types: reg, integer, time

Vector and scalar types

2(b)(ii) Scalar vs Vector

A scalar holds a single bit (wire a;), while a vector holds multiple bits (wire [7:0] a;). Vectors are used for buses and data words.

2(c)(i) NOR gate primitive

NOR gate outputs logic 1 only when all inputs are 0.

nor (y, a, b);

2(c)(ii) 4:1 MUX gate-level code

module mux4to1(y,a,b,c,d,s0,s1); output y; input a,b,c,d,s0,s1; assign y = (~s1 & ~s0 & a) | (~s1 & s0 & b) | (s1 & ~s0 & c) | (s1 & s0 & d); endmodule

2(d)(i) Inertial and intra-assignment delays

Inertial delay: Ignores short pulses.

Intra-assignment delay: Delay specified within assignment (a = #5 b;).

2(e)(i) Blocking vs Non-blocking assignments

Blocking (=) executes sequentially, while non-blocking (<=) executes concurrently and is mainly used in sequential circuits.

2(e)(ii) JK Flip-Flop (Behavioral Model)

always @(posedge clk) case({j,k}) 2'b00: q<=q; 2'b01: q<=0; 2'b10: q<=1; 2'b11: q<=~q; endcase

2(f)(i) NMOS inverter

NMOS inverter uses NMOS transistor with pull-up load. It is modeled using switch-level primitives.

2(h)(i) Fork-join construct

fork-join allows parallel execution of statements. It is useful for modeling concurrent hardware behavior.

SECTION – C (Very Long Answer Questions)

(Attempt any TWO – 2 × 15 = 30 Marks)

3(i) FSM to detect 1001 sequence (Mealy Machine)

A Mealy machine produces output based on current state and input.
States are designed to track partial sequence detection. Output becomes 1 immediately after detecting 1001.