THEORY EXAMINATION (SEM–VI) 2016-17 COMPUTER ARCHITECTURE & ORGANIZATION

COMPUTER ARCHITECTURE & ORGANIZATION – NEC012

B.Tech (SEM VI) | Section-wise Solved Answers

SECTION – A

(Explain the following – 2 marks each)

(a) Memory

Memory is a hardware component used to store data and instructions temporarily or permanently. It plays a vital role in system performance and includes primary and secondary storage.

(b) Flash Memory

Flash memory is a non-volatile memory that retains data even when power is off. It is widely used in USB drives, SSDs, and embedded systems.

(c) IEEE

IEEE stands for Institute of Electrical and Electronics Engineers. It defines standards such as IEEE-754 for floating-point representation to ensure consistency across systems.

(d) Design Methodology

Design methodology is a structured approach used to design computer systems, starting from requirement analysis to implementation and testing.

(e) Normalization and Biasing

Normalization ensures the mantissa in floating-point numbers has a leading non-zero digit. Biasing allows both positive and negative exponents to be stored using unsigned numbers.

(f) Fixed Point Arithmetic

Fixed point arithmetic represents numbers with a fixed number of digits after the decimal point. It is simpler and faster than floating-point arithmetic but has limited range.

(g) Microcode and Microinstruction

Microcode is a set of low-level instructions stored in control memory. A microinstruction controls micro-operations within the CPU.

(h) Horizontal and Vertical Microinstructions

Horizontal microinstructions are wide and allow parallel operations, while vertical microinstructions are compact and encoded, reducing control memory size.

(i) Processor–Memory Communication

It refers to data transfer between CPU and memory using buses, control signals, and timing mechanisms such as read/write cycles.

(j) PLDs

Programmable Logic Devices are digital components that can be programmed to perform logic functions. Examples include PAL, PLA, and FPGA.

SECTION – B

(Attempt any five – explained clearly)

(a) Instruction Pipelining

Pipelining improves CPU performance by overlapping instruction execution stages such as fetch, decode, execute, and write back. It increases throughput but may introduce hazards.

(b) Cache Memory and Numerical

Cache memory is a small, fast memory placed between CPU and main memory to reduce access time.

Given:

Two-way set associative

Block size = 4 words

Cache holds 2048 words

Main memory = 128K × 32

(i) Number of blocks = 2048 / 4 = 512 blocks
Number of sets = 512 / 2 = 256 sets

(ii) Cache size = 2048 × 32 bits

(c) Combinational Array Multiplier and Booth Algorithm

Array multipliers use combinational circuits for fast multiplication. Booth’s algorithm reduces the number of additions by encoding binary numbers, making it efficient for signed multiplication.

(d) PLDs: Advantages & Design

Advantages include flexibility, reduced hardware, and fast prototyping.
Disadvantages include limited complexity and cost.

A 4-bit register with parallel I/O uses flip-flops with common clock and control signals.

(e) Error Detection and Correction

Error detection uses parity bits, while correction uses Hamming codes. ECC can detect and correct single-bit errors during data transmission.

(f) High Speed Adders

Carry Look Ahead Adders reduce delay by calculating carry signals in advance, improving speed over ripple carry adders.

(g) 8M × 8 DRAM

This DRAM chip stores 8 million locations with 8-bit data each. It uses row and column address multiplexing to reduce pin count.

(h) VHDL and Modeling

VHDL is a hardware description language used for modeling digital systems. Structural modeling describes a system using interconnected components.

SECTION – C

(Attempt any two – long answers)

(3) Microprogrammed Controller

A microprogrammed controller uses control memory to store microinstructions. The program control unit generates control signals based on instruction execution.
An accumulator-based CPU uses a state transition graph to represent instruction cycles.

(4) Microprogram Sequencer and Superscalar

The microprogram sequencer selects the next microinstruction.
Superscalar processors execute multiple instructions per clock cycle using parallel execution units.

(5) Booth Algorithm and Floating-Point Multiplication

Booth’s algorithm efficiently handles signed multiplication.
Example: 4 × (-5) is performed using Booth encoding.
Floating-point multiplication involves exponent addition, mantissa multiplication, and normalization.