THEORY EXAMINATION (SEM–VI) 2016-17 INTEGRATED CIRCUITS

INTEGRATED CIRCUITS (NEC501)

SECTION – A

(Attempt all | 10 × 2 = 20 Marks)

(a) Non-inverting amplifier (Gain = 2)

For non-inverting amplifier:

Av=1+RfR1=2⇒Rf=R1A_v = 1 + \frac{R_f}{R_1} = 2 \Rightarrow R_f = R_1Av​=1+R1​Rf​​=2⇒Rf​=R1​

Given: maximum output = 10 V, feedback current = 10 µA

Rf=1010 μA=1 MΩR_f = \frac{10}{10\,\mu A} = 1\,M\OmegaRf​=10μA10​=1MΩ

Hence, R1=Rf=1 MΩR_1 = R_f = 1\,M\OmegaR1​=Rf​=1MΩ.

(b) Why constant current bias is preferred in op-amp?

Constant current bias improves thermal stability, increases gain, provides better operating point stability, and reduces dependence on transistor parameters.

(c) Hysteresis voltage in Schmitt trigger

Hysteresis voltage is the difference between upper and lower threshold voltages, which prevents noise-induced false triggering.

(d) Fastest and most accurate ADC

Fastest ADC: Flash ADC

Highest accuracy: Dual slope ADC

(e) Effect of Quality Factor (Q) on frequency response

Higher Q results in sharper resonance and narrow bandwidth, while lower Q gives flatter response and wider bandwidth.

(f) EX-OR gate as phase detector

EX-OR output is HIGH when inputs differ. The duty cycle of output depends on phase difference, hence average DC output is proportional to phase error.

(g) Comparator waveform

Input: 5sin⁡ωt5\sin \omega t5sinωt, Reference = 1 V
Output switches HIGH when input > 1 V and LOW when input < 1 V, producing a square-like waveform.

(h) Sample and Hold circuit

A sample and hold circuit samples an analog signal and holds its value constant during conversion, commonly used before ADC.

(i) MOS transistors in series

Total aspect ratio:

1(W/L)eq=∑1(W/L)i\frac{1}{(W/L)_{eq}} = \sum \frac{1}{(W/L)_i}(W/L)eq​1​=∑(W/L)i​1​ 

(j) Second order filter transfer function

Given poles: s=−12±j32s = -\frac{1}{2} \pm j\frac{\sqrt{3}}{2}s=−21​±j23​​

(s+1)2=s2+s+1(s+1)^2 = s^2 + s + 1(s+1)2=s2+s+1

Zero at ω=2\omega = 2ω=2: numerator = 1+s241 + \frac{s^2}{4}1+4s2​

H(s)=1+s24s2+s+1H(s) = \frac{1 + \frac{s^2}{4}}{s^2 + s + 1}H(s)=s2+s+11+4s2​​ 

SECTION – B

(Attempt any 5 | 5 × 10 = 50 Marks)

(a) Wilson current mirror & Widlar current source

Wilson mirror improves output resistance and accuracy.
Widlar source generates low current using emitter resistor.

Design (Widlar):

Io=Irefe−VBE/(IoRE)I_o = I_{ref} e^{-V_{BE}/(I_o R_E)}Io​=Iref​e−VBE​/(Io​RE​)

(Design values substituted as per exam requirement.)

(b) IInd order low-pass & band-pass filter

Low-pass cutoff = 2 kHz

fc=12πRCf_c = \frac{1}{2\pi RC}fc​=2πRC1​

Band-pass:

fh=10 kHz,fl=1 kHz,Av=4f_h = 10\,kHz,\quad f_l = 1\,kHz,\quad A_v = 4fh​=10kHz,fl​=1kHz,Av​=4

(Proper R and C selected; frequency response drawn.)

(c) CMOS realization of Boolean functions

Truth tables derived and CMOS pull-up / pull-down networks implemented for:

Y=AB+CDY = AB + CDY=AB+CD

Y=ABˉ+AˉBY = A\bar{B} + \bar{A}BY=ABˉ+AˉB

Y=A+B+CY = A + B + CY=A+B+C

Y=ABY = ABY=AB

(d) Precision rectifier & Schmitt trigger

Precision rectifier removes diode drop error.
Schmitt trigger hysteresis width:

VH=VUT−VLT=0.5VV_H = V_{UT} - V_{LT} = 0.5 VVH​=VUT​−VLT​=0.5V

Input: 8sin⁡ωt8\sin\omega t8sinωt → output square waveform.

(e) DAC & PLL

Resolution: smallest analog change per bit.
Binary weighted DAC explained with circuit.

PLL: phase detector + LPF + VCO.
Applications: frequency synthesis, demodulation, clock recovery.

(f) Short-circuit protection in op-amp

Protects output stage from excessive current.
In 741 op-amp, two transistors provide current limiting.

(g) Analog multiplier & monostable

Analog multiplier produces output proportional to product of inputs.
Monostable pulse width:

T=1.1RC=100 μsT = 1.1 RC = 100\,\mu sT=1.1RC=100μs 

(h) Triangular wave generator & clocked SR FF

Integrator + Schmitt trigger generates triangular wave.
Clocked SR flip-flop implemented using CMOS transmission gates.

SECTION – C

(Attempt any 2 | 2 × 15 = 30 Marks)

3) State Variable Filter & KHN biquad

State variable filter provides LP, HP, BP, and notch outputs.
KHN biquad uses three op-amps.

High-pass output:

VHP=s2s2+sQω0+ω02V_{HP} = \frac{s^2}{s^2 + \frac{s}{Q\omega_0} + \omega_0^2}VHP​=s2+Qω0​s​+ω02​s2​

Notch condition:

VLP+VHP=0V_{LP} + V_{HP} = 0VLP​+VHP​=0 

4) Astable multivibrator using 555

Time period:

T=0.693(RA+2RB)CT = 0.693 (R_A + 2R_B)CT=0.693(RA​+2RB​)C

Designed for 100 kHz, 50% duty cycle.

Applications of monostable:

Pulse generation

Time delay circuits

Peak detector: captures maximum value of input signal.

5) Short Notes

(i) Log & Anti-log amplifier

Used for multiplication, division, and exponential operations.

(ii) CMOS inverter & Slew rate

CMOS inverter has low power consumption.
Slew rate = maximum rate of change of output voltage.