(SEM VII) THEORY EXAMINATION 2024-25 VLSI DESIGN

VLSI DESIGN (KEC072) – COMPLETE SOLVED PAPER

Time: 3 Hours  Max Marks: 100
Instructions: Attempt all Sections

SECTION A (2 × 10 = 20 Marks)

Attempt all questions in brief

a) Moore’s Law

Moore’s Law states that the number of transistors on an integrated circuit doubles approximately every 18–24 months, leading to increased performance and reduced cost per transistor.

b) Importance of critical path analysis

Critical path analysis identifies the longest delay path in a circuit. It determines the maximum operating speed and is essential for timing optimization.

c) Skin effect

Skin effect is the tendency of alternating current to flow near the surface of a conductor at high frequencies, increasing effective resistance.

d) Lumped vs Distributed RC model (transient response)

Lumped RC model: Assumes resistance and capacitance are concentrated at one point; valid for short interconnects.

Distributed RC model: Resistance and capacitance are spread along the interconnect; gives more accurate delay for long wires.

e) Charge sharing in dynamic CMOS

Charge sharing occurs when charge stored on a precharged node is redistributed to other internal nodes, causing voltage degradation.

f) Cascading of dynamic gates

Dynamic gates are cascaded using Domino logic, ensuring monotonic signal transitions and preventing incorrect discharge.

g) DRAM vs SRAM

h) Types of non-volatile memories

ROM                                                                       PROM

EPROM                                                                   EEPROM

Flash memory

i) Controllability and observability                          Controllability: Ease of setting a node to 0 or 1

Observability: Ease of observing a node’s value at output
Both are crucial for testability.

j) Fault in digital circuits

A fault is any physical or logical defect that causes a circuit to behave incorrectly.

SECTION B (10 × 3 = 30 Marks)

Attempt any three

a) VLSI design hierarchy & abstraction layers

Hierarchy:                                                                   System level

Architectural level                                                       Logic level

Circuit level                                                                 Layout level

Each layer hides complexity and improves productivity.

b) Effects of R, C, and L on interconnect performance

Resistance: Causes delay and power loss                  Capacitance: Slows signal transitions

Inductance: Causes ringing and noise

Distributed RC model captures these effects accurately.

c) Noise in dynamic CMOS design

Noise sources:                                                              Charge sharing

Clock feedthrough                                                        Leakage currents

Impact: Reduced noise margin and incorrect logic levels.

d) DRAM and SRAM operation

DRAM: Stores data as charge in capacitors, requires refresh

SRAM: Uses bistable latches, faster and more stable

e) Ad-hoc testability techniques                                   Adding test points

Partitioning logic

Improving controllability and observability                  Used to simplify testing of combinational circuits.

SECTION C (10 × 5 = 50 Marks)

Attempt one from each question

Q3(a) CMOS propagation delay & sheet resistance

Propagation delay depends on:

tp∝Rsheet×Cloadt_p \propto R_{sheet} \times C_{load}tp​∝Rsheet​×Cload​

Higher sheet resistance increases RC delay, reducing circuit speed.

Q3(b) Critical path & significance

Critical path is the longest delay path between input and output.
It limits clock frequency and determines overall performance.

Q4(a) RC delay model derivation

Interconnect delay:                                              td=0.38RCt_d = 0.38RCtd​=0.38RC

Distributed RC models give accurate transient response for long wires.

Q4(b) Parameters affecting interconnects

Wire length                                                         Width and thickness

Dielectric constant                                              Spacing

Temperature

Q5(a) Single-phase clocking problems

Charge leakage                                                   Noise sensitivity

Poor cascading                                                    Reduced reliability

Q5(b) Steady-state behavior of dynamic CMOS

In steady state, dynamic gates rely on stored charge, making them sensitive to leakage and noise.

Q6(a) Volatile vs Non-volatile memories

Q6(b) Power consumption in CMOS

P=αCV2fP = \alpha C V^2 fP=αCV2f

Voltage scaling significantly reduces dynamic power, improving efficiency.

Q7(a) Common faults in digital circuits

Stuck-at-0 / Stuck-at-1                                        Bridging faults

Open faults                                                          These cause incorrect logic behavior.

Q7(b) Functional fault modeling

Logic level: Boolean fault models                       Register level: Data path and control faults

Used for systematic testing and diagnosis.