(SEM VII) THEORY EXAMINATION 2024-25 ADVANCED MICRO PROCESSORS & MICRO CONTROLLERS

KEE070 – ADVANCED MICROPROCESSORS & MICROCONTROLLERS

Complete Solved Question Paper

SECTION A

(Attempt all questions – 2 × 10 = 20 marks)

Q1(a) Define pipelining

Pipelining is a technique in which the execution of an instruction is divided into stages and multiple instructions are executed simultaneously, one in each stage, to improve CPU throughput.

Q1(b) Physical address formation in 8086

Physical address is formed using:

Physical Address=(Segment Register×10H)+Offset\text{Physical Address} = (\text{Segment Register} \times 10H) + \text{Offset}Physical Address=(Segment Register×10H)+Offset

Example:
CS = 2000H, IP = 1234H
Physical Address = 20000H + 1234H = 21234H

Q1(c) AL content after ADD & AAA

Given:                                                     AL = 35H
BL = 39H

Step 1: ADD AL, BL                                35H + 39H = 6EH

Step 2: AAA                                           Since lower nibble > 9:

AL = AL + 06H = 74H                            Upper nibble cleared

Final AL = 04H

Q1(d) Addressing modes of 8086

Immediate                                             Register

Direct                                                     Register indirect

Based                                                     Indexed

Based indexed                                       Relative

Q1(e) 8255 ports usage

Port A: Used in all modes                     Port C: Used for handshake and control signals

Q1(f) Control word format of 8255 (I/O mode)

D7 = 1 (I/O mode)                                 D6–D5 = Mode selection for Group A

D4 = Port A direction                             D3 = Port C upper direction

D2 = Mode selection for Group B          D1 = Port B direction

D0 = Port C lower direction

Q1(g & h) Features of ARM Processor

RISC architecture                                    Low power consumption

Pipeline execution                                  Large register set

Conditional execution                            High performance per watt

Q1(i & j) MSP430 exceptions

Reset                                                      Non-maskable interrupt (NMI)

Maskable interrupts                               Watchdog timer interrupt
Used for handling abnormal or priority events.

SECTION B

(Attempt any three – 10 × 3 = 30 marks)

Q2(a) Pin diagram of 8086

8086 has 40 pins, grouped as:              Address/Data pins (AD0–AD15)

Control signals (RD, WR, ALE)                Interrupt pins (INTR, NMI)

Mode select (MN/MX)                           Power & clock pins

Used to interface memory and I/O devices.

Q2(b) Instruction sets of 8086 & Branch instructions

Types of instruction sets:

Data transfer                                          Arithmetic

Logical                                                   Branch

Loop                                                      String

Flag manipulation

Branch instruction examples:

JMP LABEL                                             JZ LABEL

JNZ LABEL                                             JC LABEL

Used to alter program flow.

Q2(c) Interfacing 8255 with 8086

8255 mapped as I/O device                 Connected using data bus D0–D7

A0, A1 select ports                               RD & WR control read/write

Used for parallel I/O operations

Q2(d) Real mode vs Protected mode

Q2(e) MSP430 instruction set                        Arithmetic: ADD, SUB, INC

Logical: AND, OR, XOR                                      Data transfer: MOV

Control: JMP, CALL, RET

Example:                                                            ADD R4, R5

SECTION C

Q3(a) Register organization of 8086

Registers:                                                         General purpose: AX, BX, CX, DX

Segment: CS, DS, SS, ES                                    Pointer: SP, BP

Index: SI, DI                                                       Flag register

Applications:                                                   AX: Arithmetic

BX: Base addressing                                          CX: Loop counter

DX: I/O operations

Q3(b) Read & Write cycle timing (Minimum mode)

Read Cycle:                                                      ALE high → address latched

RD low → memory read                                    Data available on bus

Write Cycle:                                                     ALE high

WR low → data written

Q4(a) Instruction set of 8086

Data transfer                                                     Arithmetic

Logical                                                              Control transfer

String manipulation                                          Flag manipulation

Q4(b) AAA, DAA, DAS

AAA: Adjust after ASCII addition                     DAA: Adjust after BCD addition

DAS: Adjust after BCD subtraction

Q5(a) Modes of operation of 8253

Mode 0: Interrupt on terminal count               Mode 1: Hardware retriggerable

Mode 2: Rate generator                                   Mode 3: Square wave generator

Mode 4: Software triggered strobe                  Mode 5: Hardware triggered strobe

Q5(b) Pin diagram of 8259 PIC

IR0–IR7: Interrupt requests                              INT: Interrupt output

INTA: Interrupt acknowledge                           Data bus pins
Used for interrupt management.

Q6(a) Block diagram of ARM processor

Register bank                                                   ALU

Barrel shifter                                                    Control unit

Pipeline stages (Fetch, Decode, Execute)

Q6(b) 80286 block diagram

Bus unit                                                           Execution unit

Memory management unit                             Protection unit

Supports protected mode operation.

Q7(a) MSP430 instruction set

Arithmetic: ADD, SUB, INC                             Flow control: JMP, CALL, RET

Q7(b) MSP430 architecture

CPU core                                                          Flash memory

RAM                                                                 Timers

ADC                                                                  I/O ports

Low-power modes                                           Optimized for ultra-low power applications.