(SEM VII) THEORY EXAMINATION 2022-23 VLSI DESIGN

SECTION A (2 Marks Each)

(a) Critical Path

The critical path is the longest delay path in a circuit that determines the maximum operating speed of the system.

(b) Sheet Resistance

Sheet resistance is the resistance of a thin film of material having unit length and unit width, expressed in ohms per square (Ω/□).

(c) Scaling

Scaling is the process of reducing the size of MOS transistors and interconnects to increase speed, density, and reduce power consumption.

(d) Delay in Any Circuit

Delay is the time taken by a signal to propagate from input to output of a circuit.

(e) Cascade Circuit

A cascade circuit is formed when multiple logic gates are connected in series, where output of one gate is input to the next.

(f) Combinational vs Sequential Circuits

Combinational circuits depend only on present inputs, while sequential circuits depend on present inputs and past states (memory).

(g) Semiconductor Memory

Semiconductor memory is a memory device made using integrated circuits, such as RAM and ROM, to store digital data.

(h) Low-Power Circuit

A low-power circuit is designed to minimize power consumption while maintaining required performance.

(i) Defects

Defects are physical imperfections introduced during fabrication that may cause circuit malfunction.

(j) Testability

Testability refers to the ease with which faults in a VLSI circuit can be detected and diagnosed.

SECTION B (10 Marks Each – Attempt Any Three)

(a) Design Methodologies Used in VLSI Design

VLSI design methodologies include full-custom design, standard cell design, gate-array design, and FPGA-based design. Full-custom offers highest performance but is costly. Standard cell design balances performance and cost. Gate-array design reduces design time. FPGA design provides flexibility and rapid prototyping.

(b) Linear Delay Model in VLSI Design

The linear delay model represents delay as a function of load capacitance and intrinsic gate delay. It helps in estimating propagation delay and is widely used for timing analysis in digital VLSI circuits.

(c) Noise in VLSI and Noise Margins

Noise is any undesired disturbance that affects signal integrity. Noise margins define tolerance limits.
Noise Margin High (NMH) and Noise Margin Low (NML) indicate the circuit’s ability to withstand noise without logic errors.

(d) Types of Power Dissipation in VLSI Circuits

Power dissipation includes dynamic power (switching activity), static power (leakage currents), and short-circuit power. Reducing power dissipation is critical in modern VLSI systems.

(e) Types of Faults in VLSI Circuits

Faults include stuck-at faults, bridging faults, open faults, delay faults, and transient faults. Fault modeling helps in effective testing and fault detection.

 SECTION C (10 Marks Each)

Q3

(a) Moore’s Law and Evolution of VLSI

Moore’s Law states that the number of transistors on a chip doubles approximately every 18–24 months.
Evolution stages include SSI, MSI, LSI, VLSI, and ULSI, leading to modern high-performance processors and SoCs.

(b) Y-Chart VLSI Design Flow

The Y-chart has three arms:
• Behavioral domain – describes functionality
• Structural domain – describes components and interconnections
• Physical domain – describes layout and geometry
Design proceeds from system level to layout level.

Q4

(a) Logical Effort and Logical Effort of 2-Input NOR

Logical effort measures the ability of a gate to drive load compared to an inverter.
For a 2-input CMOS NOR gate, logical effort is greater than 1, indicating higher delay compared to inverter due to series PMOS transistors.

(b) Types of Scaling in VLSI

Scaling types include constant field scaling, constant voltage scaling, and general scaling. Scaling improves speed, reduces power, and increases integration density.

Q5

(a) CMOS Layout of 2-Input AND Gate

A CMOS AND gate is implemented using a NAND gate followed by an inverter. PMOS transistors are connected in parallel and NMOS in series for NAND operation. (Neat diagram required in exam)

(b) np-CMOS Logic

np-CMOS logic uses both NMOS and PMOS networks for logic implementation.
Advantages include high speed and good noise margin.
Applications include high-performance digital circuits.

Q6

(a) Working and Applications of 6-T SRAM Cell

A 6-T SRAM cell uses two cross-coupled inverters and two access transistors. It provides fast access and low power. Used in cache memory and register files.

(b) Types of ROM Cells

ROM types include Mask ROM, PROM, EPROM, and EEPROM. Each differs in programmability and erase capability.

Q7

(a) Ad-Hoc Testing Technique

Ad-Hoc testing uses external test patterns and observation points without built-in hardware. It is simple but limited in fault coverage.

(b) Built-In Self-Test (BIST)

BIST integrates test pattern generation and response analysis within the chip.
Advantages include faster testing, reduced external hardware, and high fault coverage.