SECTION A – Explanation
Section A of the VLSI Design paper is meant to test the student’s basic conceptual understanding of VLSI fundamentals, CMOS logic, power, and interconnect concepts. All questions in this section are compulsory and require brief but technically correct answers. The examiner mainly checks whether the student understands the core ideas that form the foundation of VLSI system design.
The questions in this section include Moore’s law in reference to VLSI design, implementation of EX-OR gate using CMOS logic, difference between static and dynamic power consumption, meaning of interconnect impact, advantages of dynamic logic circuits over static logic, overview of power consumption in CMOS logic circuits, and definition of interconnect delay. These topics represent the basic building blocks of VLSI design.
For example, Moore’s law tests understanding of technology scaling and transistor density growth. The CMOS EX-OR gate question checks logic realization skills. Power-related questions evaluate awareness of switching power, leakage power, and short-circuit power, which are critical issues in modern VLSI.
Interconnect impact and delay questions test understanding that performance is no longer limited only by transistors but also by wiring. Answers in this section should be short, accurate, and written in correct VLSI terminology. Lengthy explanations are not required, but conceptual mistakes can easily reduce marks.
SECTION B – Explanation
Section B evaluates the student’s conceptual clarity, design understanding, and ability to explain VLSI fabrication, interconnects, logic implementation, and low-power techniques. Students are required to attempt any three questions, which allows them to choose questions according to their preparation strength. The questions in this section require descriptive answers and, in some cases, logical design explanation.
The topics covered in Section B include CMOS fabrication steps using n-well process with diagram, RC delay model for interconnects, implementation of a given Boolean expression using logic design, advantages of interconnect modeling with calculation of resistance and capacitance, and design techniques for low-power CMOS VLSI circuits. These questions test both theoretical understanding and practical design concepts.
For example, the CMOS fabrication question requires step-by-step explanation of oxidation, diffusion, photolithography, implantation, and metallization along with a neat diagram. The RC delay model question evaluates understanding of resistance and capacitance distribution in interconnects and its effect on signal delay. Boolean expression implementation checks logic optimization and CMOS realization skills. Low-power design techniques require explanation of voltage scaling, clock gating, transistor sizing, and architectural techniques. Answers in this section should be written in a logical flow with proper explanations and diagrams wherever required. Each answer generally spans about one and a half to two pages.
SECTION C – Explanation
Section C is the most important and highest-weight section of the VLSI Design paper. This section tests the student’s in-depth understanding, analytical ability, and system-level knowledge of VLSI design concepts. Each question has internal choices, and students must attempt only one part from each question.
The questions in Section C cover advanced and application-oriented topics such as the Y-chart and VLSI design process, stick diagrams and CMOS inverter layout concepts, logical effort and electrical effort, linear RC delay model and its limitations, Elmore delay model and its merits, energy-delay product and power-delay product with low-power architectures, interconnect engineering, CMOS SRAM cell design strategy, behavior of pass transistor in dynamic CMOS logic, controllability and observability, and scan-based testing techniques.
For example, the Y-chart question tests understanding of behavioral, structural, and physical domains of VLSI design. Stick diagram questions check layout-level conceptual clarity. Delay models such as Linear RC and Elmore delay test timing analysis knowledge. SRAM cell design questions evaluate memory design fundamentals. Controllability and observability questions assess testability concepts, which are crucial in VLSI testing. Answers in this section should be detailed, well-structured, and supported by neat diagrams wherever applicable. Each answer typically extends over two to three pages and plays a decisive role in the final score.
Overall Understanding of the Paper Pattern
The VLSI Design (REC-702) question paper is structured to evaluate students progressively from basic concepts to advanced design and analysis skills. Section A focuses on fundamental definitions and short conceptual understanding, Section B evaluates fabrication, interconnect, and design techniques, and Section C tests deep knowledge of VLSI design methodology, delay models, memory design, low-power architectures, and testing techniques. Students who understand this structure can prepare effectively by revising fundamentals for Section A, strengthening conceptual explanations for Section B, and mastering long descriptive and diagram-based answers for Section C.
A strong preparation strategy for this subject includes understanding CMOS fabrication, practicing delay models, revising memory and low-power design concepts, and gaining clarity on testability techniques. Section C carries the maximum weight and requires special attention to score high marks.
