(SEM VII) THEORY EXAMINATION 2019-20 VLSI DESIGN

VLSI DESIGN (REC-702)

B.Tech – Semester VII

SECTION A

(Attempt all questions)

(a) Meaning of ZpdZ_{pd}Zpd​ and ZpuZ_{pu}Zpu​ in an inverter circuit

In a CMOS inverter, ZpdZ_{pd}Zpd​ represents the effective pull-down impedance offered by the NMOS transistor when it is ON and pulling the output node towards ground. Similarly, ZpuZ_{pu}Zpu​ represents the effective pull-up impedance offered by the PMOS transistor when it is ON and pulling the output node towards the supply voltage VDDV_{DD}VDD​. These impedances play an important role in determining the switching speed, noise margins, and power dissipation of the inverter.

(b) Circuit arrangement of a 2-input NOR gate using CMOS logic

A 2-input NOR gate using CMOS logic consists of a pull-up network made of two PMOS transistors connected in series and a pull-down network made of two NMOS transistors connected in parallel. The PMOS transistors conduct only when both inputs are low, pulling the output high. The NMOS transistors conduct when either input is high, pulling the output low. This complementary structure ensures low static power dissipation and reliable logic operation.

(c) Parasitic delay

Parasitic delay is the delay caused by unwanted capacitances and resistances present in MOS circuits. These parasitic elements arise due to junction capacitances, interconnect capacitances, and diffusion resistances. Parasitic delay becomes significant as device dimensions shrink and interconnect lengths increase. It limits circuit speed and must be carefully considered during VLSI layout design.

(d) Channel length modulation

Channel length modulation is a short-channel effect observed in MOS transistors when the effective channel length decreases with an increase in drain-to-source voltage. Due to this effect, the drain current slightly increases even in the saturation region, causing deviation from ideal transistor behavior. Channel length modulation affects gain and output resistance of MOS devices in analog and digital circuits.

(e) Implementation of 2:1 MUX using CMOS Transmission Gate

A 2:1 multiplexer using CMOS transmission gates consists of two transmission gates controlled by a select signal and its complement. Each transmission gate passes one input to the output depending on the select line. CMOS transmission gates provide bidirectional signal flow with minimal voltage drop, making them suitable for high-speed and low-power multiplexing applications.

(f) Need for low power VLSI chips

Low power VLSI chips are essential due to increasing device density, portable electronic devices, and thermal limitations. Excessive power consumption leads to heat generation, reduced battery life, and reliability issues. Low power design techniques improve energy efficiency, enable compact designs, and support modern applications such as mobile devices, IoT systems, and wearable electronics.

(g) Applications of FPGA

Field Programmable Gate Arrays are widely used in digital system design due to their flexibility and reconfigurability. They are used in prototyping ASIC designs, digital signal processing, communication systems, embedded systems, and real-time control applications. FPGAs allow rapid design changes without the need for fabrication, reducing development cost and time.

SECTION B

(Attempt any three)

(a) Fabrication process of N-MOS transistor and MOSFET capacitances

The fabrication of an N-MOS transistor begins with a p-type silicon substrate. The process involves oxidation to form a silicon dioxide layer, photolithography to define regions, ion implantation for source and drain formation, and deposition of polysilicon gate material. The gate oxide thickness and channel doping determine transistor characteristics. MOSFET capacitances arise due to gate-to-source, gate-to-drain, and gate-to-bulk interactions. These capacitances significantly affect switching speed and dynamic power consumption.

(b) Derivation of VIHV_{IH}VIH​, VILV_{IL}VIL​, NML, and NMH for CMOS inverter

In a CMOS inverter, VILV_{IL}VIL​ and VIHV_{IH}VIH​ represent the input voltage limits for correct logic recognition. Noise margins are defined as the maximum noise voltage that can be tolerated without logic error. Noise Margin Low (NML) and Noise Margin High (NMH) are derived from the voltage transfer characteristics of the inverter. High noise margins indicate better noise immunity and reliable digital operation.

(c) Domino and NORA CMOS logic circuits

Domino logic is a dynamic CMOS logic style that uses a precharge and evaluation phase to achieve high-speed operation. It is suitable for high-performance processors but requires careful clocking. NORA CMOS logic overcomes the cascading limitation of domino logic by allowing both true and complementary signals. These logic styles are used in high-speed VLSI systems where performance is critical.

SECTION C

(Attempt any one)

Short note on DRAM cell, leakage, and refresh operation

A DRAM cell consists of a single transistor and a capacitor used to store a binary value. The charge stored in the capacitor represents logic ‘1’ or ‘0’. Due to leakage currents, the stored charge gradually decays over time. To maintain data integrity, DRAM requires periodic refresh operations where the stored charge is restored. This refresh requirement makes DRAM slower than SRAM but allows much higher memory density and lower cost.

Scan-based testing and fault models

Scan-based testing improves testability of sequential circuits by converting them into combinational logic during test mode. Flip-flops are connected in a scan chain, enabling easy observation and control of internal states. Fault models such as stuck-at faults, bridging faults, and delay faults are used to identify manufacturing defects and ensure reliable circuit operation.