SECTION A
(Attempt all questions in brief – 2 × 10 = 20 marks)
(a) Why do we need low-power VLSI circuits in today’s scenario?
Low-power VLSI circuits are required because modern electronic devices are becoming smaller, faster, and mostly battery operated. High power consumption results in excessive heat generation, which affects performance and reliability. It also reduces battery life in portable devices. Low-power design helps in reducing energy consumption, improving battery backup, minimizing cooling requirements, and enabling high-density integration in modern chips used in mobiles, laptops, and IoT devices.
(b) Explain the terms packaging and testing.
Packaging is the process of enclosing an integrated circuit in a protective casing that provides mechanical protection, electrical connections, and heat dissipation. It ensures that the chip can be safely mounted on a circuit board. Testing is the process of checking whether the fabricated chip works correctly according to specifications. Testing helps detect manufacturing defects and ensures reliability before the chip is delivered to users.
(c) Define logical effort with example.
Logical effort is a technique used to estimate the delay of CMOS logic gates by comparing them with an inverter. It measures how much more effort a logic gate requires to drive a load compared to an inverter. For example, a NAND gate has higher logical effort than an inverter because it requires more input capacitance to produce the same output drive.
(d) Define the terms defects, errors, and faults.
A defect is a physical imperfection in the chip caused during manufacturing. An error is a mismatch between the expected output and the actual output of a circuit. A fault is a logical representation of a defect that causes the circuit to behave incorrectly. In simple terms, defects cause faults, and faults lead to errors.
(e) Distinguish between SRAM and DRAM.
SRAM stores data using flip-flops and does not require refreshing, making it faster but more expensive and larger in size. DRAM stores data as charge in capacitors and requires periodic refreshing, making it slower but cheaper and suitable for large memory applications.
(f) Bring out the drawbacks of dynamic logic.
Dynamic logic circuits are sensitive to noise and charge leakage. They require clocking and periodic refreshing of stored charge. Leakage currents can cause incorrect logic levels. Dynamic logic is also more complex to design compared to static CMOS logic.
(g) Explain controllability and observability.
Controllability refers to the ease with which a signal inside a circuit can be set to a desired value using input signals. Observability refers to how easily the internal state of a circuit can be observed at the output. Good controllability and observability simplify testing and fault detection.
(h) Why do we prefer CMOS transmission gates over other gates?
CMOS transmission gates are preferred because they can pass both logic ‘0’ and logic ‘1’ efficiently without voltage degradation. They have low resistance, low power consumption, and better signal integrity compared to pass transistor logic.
(i) Define the term interconnect.
Interconnect refers to the metal wiring used to connect different components and logic blocks on a VLSI chip. Interconnect delay plays a major role in determining the overall performance of modern integrated circuits.
(j) What is meant by stuck-at-1 and stuck-at-0 faults?
A stuck-at-1 fault occurs when a signal line remains permanently at logic ‘1’, regardless of input. A stuck-at-0 fault occurs when a signal line remains permanently at logic ‘0’. These faults are commonly used in fault modeling and testing.
SECTION B
(Attempt any three – 10 × 3 = 30 marks)
(a) Explain the n-well CMOS fabrication process.
The n-well CMOS fabrication process begins with a p-type silicon substrate. An n-well region is created by doping selected areas with donor impurities. This n-well is used to fabricate PMOS transistors, while NMOS transistors are formed directly on the p-type substrate. Oxide layers are grown to isolate regions, and polysilicon gates are deposited. Source and drain regions are formed by ion implantation. Finally, metal layers are added to create interconnections. This process allows both NMOS and PMOS devices on the same chip, enabling low-power CMOS operation.
(b) Explain the Elmore delay model.
The Elmore delay model is an approximate method used to estimate signal delay in RC networks, especially interconnects. It assumes that delay depends on the resistance and capacitance distribution along the signal path. The delay is calculated as the weighted sum of capacitances multiplied by the resistance through which they are charged. Although approximate, the Elmore model is simple and widely used in VLSI timing analysis.
(c) Write a short note on logical effort.
Logical effort is a delay estimation technique that separates delay into logical effort, electrical effort, and parasitic delay. It helps designers choose optimal gate sizes and logic structures. By comparing gates to an inverter, logical effort allows quick estimation of delay without detailed simulations.
SECTION C
Q6 (a) Explain read and write operation of SRAM memory cell. How is a 1-bit cell used in bigger memory systems?
An SRAM cell typically consists of six transistors forming two cross-coupled inverters and access transistors. During a write operation, the word line is activated and data is forced onto the bit lines, overwriting the stored value. During a read operation, the word line enables access and the stored value slightly changes the voltage on the bit lines, which is detected by sense amplifiers. Multiple 1-bit SRAM cells are arranged in rows and columns to form larger memory arrays.
Q6 (b) (i) Implement the Boolean function using domino CMOS logic.
Domino CMOS logic uses dynamic logic where a precharge phase charges the dynamic node, and an evaluation phase conditionally discharges it based on inputs. The given Boolean function is implemented using a network of NMOS transistors followed by a static inverter to ensure monotonic signal behavior.
Q6 (b) (ii) Explain voltage bootstrapping in CMOS logic.
Voltage bootstrapping is a technique used to increase the gate voltage above the supply voltage temporarily. This improves transistor drive strength and reduces delay. It is commonly used in dynamic logic circuits to improve performance.
Q7 (a) Explain the issues involved in Built-in Self-Test (BIST) techniques.
BIST allows a circuit to test itself without external equipment. However, it increases hardware overhead, design complexity, and power consumption. Generating high fault coverage and ensuring accurate diagnosis are major challenges. Despite this, BIST is widely used for memory testing.
Q7 (b) (i) Write a short note on adiabatic logic circuits.
Adiabatic logic reduces power dissipation by recovering energy during charging and discharging of capacitors. It uses slow and controlled voltage transitions. Although power efficient, adiabatic logic is complex and slower than conventional CMOS logic.
Q7 (b) (ii) Explain scan-based techniques.
Scan-based techniques improve testability by converting sequential circuits into combinational ones during testing. Flip-flops are connected in a scan chain, allowing internal states to be controlled and observed easily. This significantly improves fault detection.
