THEORY EXAMINATION (SEM–VIII) 2016-17 DIGITAL SYSTEM DESIGN USING VHDL

SECTION – A

Explain the following (Short Answer Type)

Generics in VHDL are used to define constant parameters that can be modified when a design is instantiated. They help make VHDL code flexible and reusable.

Concurrent statements in VHDL execute simultaneously, while sequential statements execute one after another inside a process block.

Array types store multiple elements of the same type, while record types group different data types into a single unit.

Functions return a single value and execute sequentially, whereas procedures can return multiple values using parameters.

Packages and libraries are used to store commonly used VHDL definitions and declarations so they can be reused across multiple designs.

A process is a block that contains sequential statements, while a wait statement controls the execution timing of the process.

Conditional statements such as IF are used for decision-making, while case statements select one option from multiple choices.

Structural modeling describes a design by connecting components together like a circuit diagram.

Transport delay represents actual signal delay, while delta delay is a simulation delay used to resolve signal updates.

HDL design flow includes stages such as design entry, simulation, synthesis, implementation, and testing.

Questions (Section A)

What are generics in VHDL?

Differentiate between concurrent and sequential statements.

What are array and record types?

Explain function and procedure.

What is structural modeling?

SECTION – B

Attempt any five (Long Answer Type)

UART is a communication device used for serial data transmission. It consists of transmitter, receiver, and control units. State machine charts help represent its working.

Floating-point operations include addition, subtraction, multiplication, and division. These operations follow specific steps such as exponent alignment, mantissa calculation, and normalization.

A divider in VHDL can be implemented using behavioral modeling, which describes the operation using sequential logic and arithmetic expressions.

Synthesis of VHDL code converts high-level hardware descriptions into gate-level circuits that can be implemented in hardware devices.

State graphs represent the control logic of digital systems such as binary multipliers. Behavioral VHDL models describe system functionality without focusing on hardware structure.

Compilation, elaboration, and simulation are important steps in VHDL design. Compilation checks syntax, elaboration links components, and simulation verifies functionality.

Full subtractor VHDL code uses logic equations to perform binary subtraction with borrow input and output.

Questions (Section B)

Explain the block diagram of UART.

What are floating-point operations?

Write a VHDL description of a divider.

What is VHDL synthesis?

Explain compilation and simulation in VHDL.

SECTION – C

Attempt any two (Detailed Explanation)

A 16×1 multiplexer selects one input from sixteen input lines based on select signals. It can be implemented in VHDL using case statements to describe selection logic.

An ALU performs arithmetic and logical operations such as addition, subtraction, AND, OR, and comparison. The control unit directs ALU operations based on input instructions.

FPGA is a programmable device that allows users to configure hardware after manufacturing. CPLD is similar but smaller and used for simpler applications. PLA and PAL are programmable logic devices used for implementing logic functions.

Questions (Section C)

Explain the working of a 16×1 multiplexer.

What is an ALU and how does it work?

Differentiate between FPGA, CPLD, and PLA.