(SEM III) THEORY EXAMINATION 2023-24 COMPUTER ORGANIZATION AND ARCHITECTURE

This examination evaluates a student’s understanding of computer architecture, digital design principles, processor organization, memory hierarchy, I/O mechanisms, pipelining, and data transfer techniques.
The paper is divided into three structured sections, assessing conceptual clarity, analytical ability, and technical explanation skills.

SECTION A – Short Answer Questions (14 Marks)

Seven questions × 2 marks each

This section tests essential definitions and basic concepts of COA.

Topics Covered:

1. Types of Buses in Computer Architecture

Students recall data bus, address bus, control bus, and system bus roles.

2. Types of Multipliers

Booth multiplier, array multiplier, Wallace tree multiplier etc.

3. Phases of Instruction Cycle

Fetch → Decode → Execute → Memory Access → Write Back.

4. Working of Control Unit

How the control unit interprets instructions, generates control signals, and coordinates CPU components.

5. Locality of Reference

Temporal and spatial locality; relevance to cache organization.

6. 2½ D Memory Organization

Stacked memory layers enabling high bandwidth and reduced latency.

7. Synchronous vs Asynchronous Serial Data Transfer

Difference in timing, clock dependency, and communication reliability.

This section checks conceptual accuracy and familiarity with fundamental COA terminologies.

SECTION B – Application-Based Analytical Questions (21 Marks)

Attempt any three × 7 marks

These questions require detailed explanations, computations, and design-level thinking.

1. Bus Arbitration & Daisy Chaining

Definition, need for bus arbitration, priority resolution, and implementation of Daisy-Chaining method.

2. Booth’s Multiplication Algorithm

Perform signed multiplication using Booth’s algorithm for:
(-12) × (-18)
Show step-by-step encoding, bit operations, partial products, and final result.

3. Pipelining

Meaning, advantages, hazards, and detailed explanation of pipeline stages such as:
IF → ID → EX → MEM → WB.

4. Memory Classification & Magnetic Disk

Memory types—sequential, direct, associative, random.
Explain construction of magnetic disk, platters, read/write heads, tracks, sectors, seek time, latency & access time.

5. Interrupt Initiated I/O vs Programmed I/O

Difference in CPU involvement, response time, overhead, and efficiency.

This section evaluates the student’s understanding of logical operations within computer systems.

SECTION C – Long Descriptive / Higher-Order Questions (35 Marks)

One question from each group × 7 marks

3. Processor Organization / Memory Stack vs Register Stack

Option A – Processor Organization

Explain CPU structure, single accumulator organization, general register organization, and stack organization with diagrams.

Option B – Memory Stack vs Register Stack

Difference in implementation, speed, access pattern, and CPU usage.

4. CLA Adder / IEEE Floating-Point Representation

Option A – Carry Look Ahead Adder

Explain carry propagation, generate & propagate signals, logic for 4-bit CLA adder, and block diagram.

Option B – IEEE-754 Single Precision Representation

Convert decimal numbers to 32-bit IEEE floating point:
(i) 85.125
(ii) -307.1875
Show binary, exponent biasing, mantissa, and sign bit.

5. Instruction Execution Cycles / Control Unit

Option A – Instruction Cycle

Explain Fetch, Decode, Operand Fetch, Execution, and Result Storage phases.

Option B – Hardwired vs Microprogrammed CU

Concept, structure, speed differences; detail components of hardwired CU.

6. Cache Mapping / Direct Mapping

Option A – Cache–Main Memory Mapping

Given M1: 16K, M2: 1M, 8-word blocks, 256-word set associative:
• Explain mapping
• Calculate effective access time for hit ratio = 0.95.

Option B – Direct Mapping Technique

With memory = 64k×16 and cache = 1k words, block size = 4 words:
• Identify bits for tag, block, word
• Calculate number of blocks in cache.

7. Asynchronous Transfer / DMA & Other Modes

Option A – Asynchronous Data Transfer

Explain strobe control, source-initiated strobe, destination-initiated strobe, and handshaking.

Option B – Data Transfer Modes

Programmed I/O, Interrupt-driven I/O, DMA.
Explain why DMA is fastest and CPU-independent.