(SEM III) THEORY EXAMINATION 2020-21 COMPUTER ORGANIZATION AND ARCHITECTURE

This is the B.Tech Semester III theory examination paper for Computer Organization and Architecture (COA).
The question paper carries 100 marks and comprehensively evaluates a student’s understanding of:

Computer architecture & organization

CPU design                                           ALU operations

Memory hierarchy                                Instruction cycle

Floating point arithmetic                     DMA & data transfer

Page replacement                                Microprogramming

Addressing modes                               Bus systems

Multiplication/Division algorithms

The paper is divided into three sections – A, B, and C, combining definitions, descriptive answers, design questions, numerical logic problems, and algorithmic applications.

SECTION A – Short Answer Questions (20 Marks)

This section contains 10 compulsory questions (2 marks each) covering:

Definition of computer architecture vs organization                   Bus arbitration & its types

Biasing in floating-point representation                                      Restoring method of division

Micro-operation & microcode                                                     RISC features

Hit ratio in cache memory                                                            Page fault

Cycle stealing in DMA                                                                  Vector interrupt

SECTION B – Descriptive / Analytical Questions (30 Marks)

Students must attempt any three out of five questions, each worth 10 marks.

Topics include:

Bus System Design

Drawing a 4-register, 4-bit bus system using multiplexers

Arithmetic expression evaluation using a zero-address stack-based machine

Carry Look-Ahead Adder

Principle + design of 4-bit CLA

Instruction Cycle

Flowchart + diagram of fetch–decode–execute cycle

2D RAM & 2.5D RAM

Diagram & explanation

DMA Controller

Block diagram and working of a typical DMA controller

SECTION C – Long / Technical Problem-Solving Questions (50 Marks)

There are five major questions (Q3–Q7); each contains two alternatives, and students must attempt one from each.

Q3 – Addressing Modes / Processor Organization

Evaluate effective address using:
Direct, Immediate, Relative, Register Indirect, Indexed modes
OR

Processor organization & types (Single bus, Multi-bus, Stack, GPR)

Q4 – Arithmetic Algorithms / IEEE Floating Point

Booth’s algorithm for multiplication of (20) × (–19)
OR

IEEE-754 floating point representation of –1460.125 in single & double precision

Q5 – Microprogramming / Control Unit

Microprogram sequencer: block diagram + working
OR

Hardwired vs Microprogrammed control unit + components

Q6 – Paging & Memory Chips

LRU & FIFO page replacement (for page string given on page 2)
Frames = 4
OR

Memory chip calculations for 1024×1 cell RAM:

Chips required for 1024×8

Chips required for 16 KB memory

Q7 – Data Transfer Modes

Asynchronous data transfer, strobe control & handshaking
OR

Different modes of data transfer (Programmed I/O, Interrupt-driven I/O, DMA modes)