(SEM-III) THEORY EXAMINATION 2019-20 COMPUTER ORGANIZATION AND ARCHITECTURE

This document is the B.Tech Semester III (2019–20) Theory Examination question paper for Computer Organization and Architecture (KCS302) under Dr. A.P.J. Abdul Kalam Technical University (AKTU).
The uploaded file contains two pages, clearly divided into three sections: SECTION A, SECTION B, and SECTION C.
The total marks are 100, and the exam duration is 3 hours.

The paper checks a student’s understanding of computer architecture concepts such as arithmetic operations, memory organization, I/O control, pipelining, microprogramming, cache mapping, floating-point representation, and Booth’s multiplication algorithm.

SECTION A — Short Answer Questions (10 × 2 = 20 Marks)

Visible on Page 1, this section contains 10 short questions, each worth 2 marks, covering fundamental definitions and basic computational operations.

The questions include:

Definition of Computer Architecture

Drawing basic functional units of a computer

Performing 2’s complement subtraction

Role of Multiplexer and Decoder

Difference between RISC and CISC

Types of microinstructions

Difference between SRAM and DRAM

Difference between 2D & 2 ½ D memory organization

Meaning of I/O control

Definition of arbitration

These questions test clarity of basic concepts and theoretical understanding.

SECTION B — Descriptive Questions (Attempt Any 3 × 10 = 30 Marks)

This section is also on Page 1.
There are five long questions, and students must attempt any three.

Topics include:

Minimizing gate propagation delay using AND/OR gates

Stored program organization with explanation

Instruction formats and types

Bus transfer using registers

Hardwired vs. Microprogrammed Control Units

These questions require detailed explanation, diagrams, and conceptual clarity.

SECTION C — Advanced / Numerical / Application-Based Questions (Q4–Q6)

Section C is spread across Page 1 and Page 2.
Students must attempt one part (a or b) from each question number.

Q4 — Floating-Point Representation / Booth Multiplication

(Located on Page 2)

Converting decimal numbers (65.175)\₁₀ and (−307.1875)\₁₀ into IEEE 32-bit single-precision format
OR

Performing Booth’s algorithm multiplication for the 6-bit numbers

Q5 — Parallelism & Microprogramming

(Page 2)

Explaining parallelism and pipelining
OR

Organization of Microprogrammed Control Unit with block diagram

Q6 — Cache Mapping & RAM Organization

(Page 2)

Different cache mapping techniques with merits and demerits
OR

RAM chip structure: given a 4096 × 8-bit chip, drawing its block diagram, pins needed, and main features of Random Access Memory

OVERALL SUMMARY OF THE DOCUMENT

The uploaded Computer Organization and Architecture (KCS302) question paper comprehensively evaluates:

Computer architecture fundamentals

Number representation & arithmetic algorithms

Instruction formats and CPU organization

Microprogramming and hardwired control

Memory hierarchy, cache mapping, RAM structure

Floating-point format (IEEE-754 single precision)

Booth’s multiplication algorithm

Pipelining and parallelism

Multiplexers, decoders, I/O control, arbitration

The format strictly follows AKTU pattern:

SECTION A: Short conceptual recall

SECTION B: Medium-length theoretical explanations

SECTION C: Numerical + applied architecture problems

The paper spans 2 pages, includes tables, diagrams, and clear formatting for marks and CO mapping.