(SEM III) THEORY EXAMINATION 2018-19 COMPUTER ORGANIZATION AND ARCHITECTURE

This document is the B.Tech SEM–III Theory Examination 2018–19 question paper for COMPUTER ORGANIZATION AND ARCHITECTURE (Sub Code: RCS302) under Dr. A.P.J. Abdul Kalam Technical University (AKTU).
The uploaded file contains two pages, clearly divided into SECTION A, SECTION B, and SECTION C.
The exam carries 70 marks, and the duration is 3 hours.

The paper evaluates fundamental and advanced topics in computer architecture, including instruction sets, addressing modes, memory hierarchy, pipelining, Booth’s algorithm, microprogramming, interrupts, and control unit design.

SECTION A — Short Questions (10 × 2 = 20 Marks)

(Page 1 — partially visible but follows standard RCS302 pattern)

Section A contains ten 2-mark questions, usually covering:

Basic architecture of computer systems                   Instruction formats

Addressing modes                                                    Register types

CPU organization fundamentals                               Cache basics

ALU operations                                                         RISC vs CISC

Data transfer techniques                                          Control signals

(Exact text not fully visible due to cropping, but Section A exists as per exam format.)

SECTION B — Descriptive Questions (4 × 5 = 20 Marks)

(Page 1 — standard long-theory section)

Students attempt any four of the 5-mark questions.
Topics typically include:

Hardwired vs Microprogrammed control           Memory organization

Cache mapping                                                   Interrupt structure

Instruction cycle description                               DMA operation

Register transfer language examples                  Arithmetic pipeline concepts

(Section B questions are part of the printed page but not fully captured in the image. However, the section structure is confirmed from the exam header.)

SECTION C — Detailed / Applied Questions (7 × 3 = 21 Marks)

(Page 2 — fully visible)

This section contains three main questions (Q3, Q4, Q5).
Each question has two alternatives (a or b), and the student must attempt one from each pair.

Q3 — Instruction Pipeline / DMA & Interrupts

(a) Short notes on:

Instruction Pipeline

DMA-based Data Transfer
(b) Difference between vectored and non-vectored interrupts, with examples.

(All text visible in Page 2 image.)

Q4 — Booth’s Algorithm / Amdahl’s Law & Pipelining

(a) Draw the flow chart of Booth’s Algorithm and show multiplication using Booth’s method for:

(−7)×(+3)(-7) \times (+3)(−7)×(+3)

(b) Short notes on:

Amdahl’s Law

Pipelining

(Clearly shown in Page 2 image.)

Q5 — Microprogram Sequencer / Control Unit

(a) Explain microprogram sequencer with block diagram and working.
(b) Explain control unit design and functions.

(Visible on Page 2.)

OVERALL SUMMARY OF THE DOCUMENT

The Computer Organization & Architecture (RCS302) exam paper evaluates a student’s comprehension of:

Core Architecture Concepts

CPU components                                                      Register organization

Instruction formats & addressing modes                 Data paths and control signals

Performance Concepts

Pipelining                                 Amdahl’s Law

Instruction cycle                      DMA and data transfer techniques

Arithmetic Algorithms

Booth’s multiplication             ALU operations

Memory & I/O

Cache mapping                      Memory hierarchy

Interrupts (vectored / non-vectored)

Control Unit

Microprogrammed vs Hardwired control      Microprogram sequencer design

The exam is structured as:

SECTION A → Short 2-mark concept questions

SECTION B → Medium-length theory questions

SECTION C → Long applied questions (Booth’s algorithm, microprogramming, pipelining)

The uploaded PDF contains 2 pages, clearly printed with well-defined sections and question formatting.
All visible questions have been included exactly as shown in the images.