(SEM-III) THEORY EXAMINATION, 2018-19 DIGITAL LOGIC DESIGN

B.Tech Engineering 0 downloads

₹29.00

The uploaded file is a B.Tech (Semester III) Theory Examination – 2018–2019 question paper for the subject DIGITAL LOGIC DESIGN, with Sub Code REC301. It is an official university exam document consisting of 2 printed pages and carries a total of 70 marks. The examination duration is 3 hours, and students are instructed to be precise, especially when solving numerical questions.

The paper evaluates a student's conceptual, analytical, and problem-solving skills in various digital electronics and logic design topics. It is structured into three sections (A, B, and C), progressively increasing in complexity—from basic definitions to detailed circuit design.

PAGE 1 OVERVIEW

Page 1 contains the exam header, instructions, and SECTION-A & SECTION-B of the paper.

SECTION-A (Short Questions) – 2 × 7 = 14 Marks

Students must “attempt all” seven short questions. These are concept-based definitions and small calculations covering:

Modulus of a counter

Flip-flop requirement for Mod-5 Ring and Mod-5 Johnson counters

Base-X logarithmic calculations (e.g., logₓ(193))

Gray code vs binary code advantage

Fan-out & fan-in definitions

Parity checking

Race-around condition

This section tests quick recall of digital logic fundamentals as expected in engineering curricula.

SECTION-B (Descriptive Questions) – 7 × 3 = 21 Marks

This part requires students to attempt any three questions, each demanding detailed explanations, derivations, or comparison-based answers.

Typical topics asked (based on visible patterns in the paper) include:

Boolean algebra Logic simplification

Karnaugh maps Decoders, multiplexers, flip-flops, counters

Sequential vs combinational circuits

This section evaluates the understanding of logic components, mathematical representations, and simplification methods.

PAGE 2 OVERVIEW

Page 2 contains SECTION-C which includes long, application-oriented circuit problems.

SECTION-C (Design/Problem-Solving Questions) – 7 Marks Each

Each question has sub-parts and students must attempt any one option from each question number. This section focuses heavily on circuit design, diagram drawing, state tables, logic equations, and error detection.

Two key questions visible on Page 2:

Question 6: Asynchronous Sequential Circuit + Parity + Subtractor Design

This question contains advanced sub-parts:

(a) A sequential logic circuit is described with:

Excitation/output equations

Y = X₁ X₂ + (X₁ + X₂)Y

Z = Y

Students must perform multiple tasks:

Draw the logic diagram of the asynchronous circuit.

Derive the transition table and output map.

Explain the behavior of the circuit.

(b) Parity error correction

Given the code 101011010, with four parity bits and odd parity usage, correct any errors.

(c) Draw a full subtractor circuit using only NAND gates.

This question tests design thinking, error analysis, and gate-level circuit implementation.

Question 7: State Table and State Diagram

Students must:

Derive the state table.

Derive the state diagram for the given sequential circuit, shown in the image on Page 2.
The diagram includes flip-flops, logic gates, and feedback loops, requiring interpretation of:

Next state equations

Input/output relationships

State transitions

This tests a student’s ability to interpret and translate sequential circuits into formal tables and diagrams.

OVERALL DOCUMENT SUMMARY

The DIGITAL LOGIC DESIGN exam paper is a complete assessment tool that covers the entire spectrum of digital electronics, including:

Basic concepts Counter design

Logic families Boolean mathematics

Sequential circuit analysis Parity and error checking

State machine derivation Gate-level implementation of arithmetic circuits

It is ideal for:

B.Tech students preparing for university exams

Competitive exam preparation (ECE/EE/CS streams)