(SEM IV) THEORY EXAMINATION 2022-23 DIGITAL ELECTRONICS

This question paper belongs to B.Tech Semester IV – Digital Electronics (KEE-401).
It carries 100 marks and the duration is 3 hours.

The exam evaluates a student's understanding of:                  Boolean algebra

Logic gates and their implementations                                   Combinational circuits

Sequential circuits                                                                    Flip-flops, counters, registers

CMOS/DTL logic families                                                         State diagrams, FSM design

The paper is divided into three sections: A, B, and C, each testing different levels of knowledge.

2. Section A – Short Answer / Conceptual Questions (20 Marks)

Section A contains 10 brief questions, each of 2 marks, covering essential definitions and conceptual clarity.

Topics involved include:

● Duality Principle

Explaining Boolean duality + proving AND (positive logic) ≡ OR (negative logic).

● EX-NOR Gate Implementation

Understanding EX-NOR logic and realizing it using minimum NOR gates.

● Half Adder

Explaining sum & carry logic, and designing using NAND gates.

● Combinational vs Sequential Circuits

Differences based on memory, timing, and output dependency.

● Synchronous vs Asynchronous Circuits

Clock dependency, hazards, timing issues.

● Multivibrators

Astable & Bistable operations.

● PISO Shift Register

Parallel-in, serial-out working concept.

● Static & Dynamic Hazards

Glitches caused by circuit propagation delays.

● Noise Margin

Tolerance range of logic levels.

● Advantages of CMOS

Low power, high noise immunity, scalability.

This section checks the basic theoretical foundation of Digital Electronics.

3. Section B – Long Answer / Analytical Questions (30 Marks)

Students must attempt any three (3) questions.
Each question carries 10 marks, requiring detailed explanation, diagrams, and calculations.

This section covers:

● Boolean Expression Simplification

K-map based simplification for a 5-variable function.

● 1:8 Demux using 1:2 Demux

Hierarchical implementation + truth tables.

● Race-Around Condition

Explaining J-K flip-flop issues and Master-Slave solution.

● Sequential Circuit Design (State Diagram)

Creating a flip-flop-based FSM for given cases.

● CMOS & DTL NOR Gate

Design + working explanation in two logic families.

This section tests design skills, logic minimization, and deep understanding of circuits.

4. Section C – Application-Based / Advanced Questions (50 Marks)

This section contains five parts, and students must attempt one question per part.
Each part carries 10 marks, focusing on practical and design-oriented topics.

Part 3 – Gate Realization & Code Conversion

Choice between:

● Implementing Basic Gates Using NAND

Building NOT, AND, OR, XOR, XNOR, NOR using only 2-input NAND.

OR

● Binary to Gray Code Conversion

4-bit code conversion + implementation using EX-OR gates.

Part 4 – Magnitude Comparator / MUX Implementation

Choice between:

● 4-bit Magnitude Comparator

Designing a logic circuit to compare two numbers.

OR

● Boolean Function using 8:1 MUX

Using A, C, D as select lines to realize the given function.

Part 5 – Flip-Flop Conversions / Counter Design

Choice between:

● Converting JK → SR, T, D

Flip-flop conversion with state tables.

OR

● MOD-12 Down Counter

Designing using T flip-flops.

Part 6 – FSM Design

Choice between:

● State Transition Table + Diagram

From given sequential logic expressions.

OR

● 3-bit Synchronous FSM

Count sequence: 0 → 1 → 3 → 7 → 4 → 2 → 0 using D flip-flops.

Part 7 – Logic Families & Memory

Choice between:

● Propagation Delay

Explaining tPHL & tPLH and why tPLH > tPHL.

OR

● ROM Types + 4-T SRAM Cell

Explanation + MOSFET-based implementation.

This section evaluates practical circuit design, state machines, timing concepts, and memory structures.

Final Summary (Purpose of WHAT DESCRIPTION)

This WHAT DESCRIPTION provides a complete, detailed explanation of:

What the question paper contains

What each section asks

How many marks each part carries

What topics students must understand

The overall structure and purpose of the exam

It is a clear, long, section-wise guide to the DIGITAL ELECTRONICS paper.