THEORY EXAMINATION (SEM–IV) 2016-17 COMPUTER ARCHITECTURE & ORGANIZATION

Subject: Computer Architecture & Organization (EEC402)

Exam Type: Theory
Semester: 4th
Time: 3 Hours
Maximum Marks: 100

Section A — Short Questions (10 × 2 = 20 Marks)

This section tests your understanding of basic computer architecture concepts through short, two-mark questions.

It includes questions like:

Explaining computer performance measures such as MIPS, throughput, and CPI.

Designing a full adder using half adders.

Explaining the IEEE 754 standard for 32-bit floating-point representation.

Defining effective address, normalization, and biasing in data handling.

Describing the difference between structure and behavior in digital systems.

Characteristics of vertical microinstructions.

Explaining why hardwired control units are faster than microprogrammed ones.

Concept of design levels in computer systems.

Basic understanding of multiprogramming and pipelining

Section B — Descriptive / Design-Based Questions (5 × 10 = 50 Marks)

This section focuses on system design, control mechanisms, and arithmetic operations.

The questions include:

Designing a 4-bit carry look-ahead adder and explaining how it improves speed.

Explaining bus arbitration methods — Daisy chaining, polling, and independent requesting — and comparing their reliability.

Describing addressing modes with examples.

Drawing and explaining the microprogram sequencer for control memory.

Designing a data path unit with ALU and register file.

Structure and working of an 8M × 8-bit DRAM chip.

Explaining a four-stage pipeline organization.

Differences between hardwired and microprogrammed control, along with terms like microoperation, microinstruction, microcode, and microprogram

Section C — Analytical / Long Questions (2 × 15 = 30 Marks)

This section includes numerical problems and in-depth derivations:

Booth’s Algorithm:  Explanation and example of signed number multiplication (e.g., 4 × –5).

8085 Microprocessor: Functional block diagram and detailed explanation of each component.

Short Notes (any three):

Cache memory                                                          Fixed point arithmetic

Vertical and horizontal microprogramming             RISC and CISC architectures

Key Topics Covered

Computer performance analysis

Control unit design (hardwired and microprogrammed)

Arithmetic operations (adder design, Booth’s algorithm)

Memory hierarchy and architecture (DRAM, cache)

Pipelining and bus organization

8085 microprocessor architecture

Purpose of the Paper

This paper tests both theoretical concepts and design understanding of how a computer system’s hardware, memory, and control units are organized and optimized for performance.