THEORY EXAMINATION (SEM–IV) 2016-17 ELECTRONIC CIRCUITS

Subject: Electronic Circuits (EEC401)

Exam Type: Theory
Semester: IV (4th Semester)
Session: 2016–17
Time: 3 Hours
Maximum Marks: 100

Section A – Short Answer Questions (10 × 2 = 20 Marks)

This section tests core understanding of operational amplifiers, feedback amplifiers, oscillators, and transistor models.

Topics Covered:

Slew Rate Calculation: Find maximum gain of an op-amp with a given slew rate and sinusoidal input.

Integrator Circuit: Draw circuit and derive its output expression.

Op-Amp Parameters: Define Slew Rate and CMRR (Common Mode Rejection Ratio).

Transistor Models: Draw the Hybrid-π and T-model equivalents of an NPN transistor.

Barkhausen Criterion: State and explain the condition for sustained oscillations.

MOSFET Operating Regions: Describe triode and saturation conditions for NMOS and PMOS transistors.

Negative Feedback: Given an amplifier gain and bandwidth, compute new gain and bandwidth with 4% feedback and find feedback ratio when bandwidth = 1 MHz.

Colpitts Oscillator: Draw the circuit, give frequency formula and oscillation condition.

Crystal Oscillator: State the working principle.

Internal Capacitances of BJT: Identify and explain their effects on frequency response.

Section B – Descriptive / Analytical Questions (5 × 10 = 50 Marks)

This section focuses on amplifier analysis, feedback networks, oscillator design, and MOSFET operation.

Key Questions Include:

Inverting Amplifier: Derive expression for closed-loop gain assuming finite open-loop gain.

Series-Series Feedback Amplifier: Perform analysis to derive gain, input, and output resistance.

RC Phase-Shift Oscillator (Op-Amp Based): Derive formula for oscillation frequency and stability conditions.

Hartley Oscillator & MOSFET Comparison:

(i) Explain Hartley oscillator with working principle.

(ii) Differentiate between DMOSFET and EMOSFET types.

BJT Biasing Analysis: Derive Q-point and stability factor expressions for an NPN transistor DC bias circuit.

MOS Differential Pair Analysis: Derive differential and common-mode gain for small-signal operation.

NMOS Operation Region Problem:

For Vt=0.7VV_t = 0.7VVt​=0.7V, VG=1.5VV_G = 1.5VVG​=1.5V, determine region of operation for
(a) VD=0.5VV_D = 0.5VVD​=0.5V, (b) 0.9V0.9V0.9V, (c) 3V3V3V.

Explain construction and working of N-type enhancement MOSFET.

Common Emitter Amplifier Characteristics:

(i) Draw input/output characteristics.

(ii) List ideal op-amp properties (infinite gain, infinite input resistance, zero output resistance, etc.).

Section C – Long Analytical Questions (2 × 15 = 30 Marks)

These questions involve detailed circuit derivations and system-level feedback analysis.

Questions Include:                    Small-Signal Analysis of Common Emitter Amplifier:
Derive expressions for:                Input resistance

Voltage gain (base to collector)  Overall voltage gain (source to load)

Open-circuit voltage gain           Output resistance

Effect of Finite Loop Gain & Bandwidth:     Explain how finite op-amp parameters affect performance.

Define input offset voltage and input offset current.

Feedback Topologies:

Explain the four feedback configurations (Voltage-Series, Voltage-Shunt, Current-Series, Current-Shunt) with block diagrams.

Explain the operation of an LC tank circuit used in oscillators.

Major Topics Covered

Op-amp circuits and parameters                                  Feedback amplifiers and topologies

BJT small-signal modeling (Hybrid-π, T-model)           Biasing and stability analysis

MOSFET operation and characteristics                         Oscillators (RC, Hartley, Colpitts, Crystal)

Frequency response and feedback effects

Purpose of the Paper

This paper evaluates students’ ability to analyze, design, and model analog electronic circuits, focusing on amplifiers, oscillators, and op-amp behavior.
It integrates theory, derivation, and numerical application, bridging semiconductor fundamentals with practical electronic circuit design.