THEORY EXAMINATION (SEM–IV) 2016-17 INTRODUTION TO MICROPROCESSOR

Course: B.Tech (Electronics / Electrical / Computer Engineering)
Subject Code: EEC406
Subject Title: Introduction to Microprocessor
Exam Type: Theory
Duration: 3 Hours
Maximum Marks: 100
Academic Year: 2016–17

SECTION – A (10 × 2 = 20 Marks)

Short conceptual questions designed to test basic understanding.

SECTION – B (5 × 10 = 50 Marks)

Descriptive and programming-based questions.

(a) Architecture of 8085

Functional Blocks: ALU, Registers (A, B, C, D, E, H, L), Program Counter, Stack Pointer, Flag Register, Instruction Register & Decoder, Timing & Control Unit.

Working: Executes instructions through fetch–decode–execute cycle.

(b) Interrupts in 8085

Hardware Interrupts: TRAP (non-maskable, highest priority), RST7.5, RST6.5, RST5.5, INTR.

Software Interrupts: RST0–RST7.

Masking: Enabled/disabled using SIM/RIM instructions.

(c) 8254 Programmable Interval Timer (PIT)

3 independent counters, 6 operating modes.

Used for time delay generation, baud rate control, event counting.

Functional blocks: Data Bus Buffer, Read/Write Logic, Control Word Register, Counters.

(d) I/O Mapped vs Memory-Mapped I/O

(e) Programmable Peripheral Interface (8255 PPI)

Ports: A, B, C (8-bit each).

Modes:

Mode 0: Simple I/O

Mode 1: Strobed I/O

Mode 2: Bidirectional

BSR (Bit Set/Reset) mode for Port C bit control.

Used for keyboards, displays, sensors.

(f) Assembly Program – Block Transfer

Ten 8-bit numbers from 2100H → 3100H

LXI H,2100H   ; Source LXI D,3100H   ; Destination MVI C,0AH     ; Counter = 10 LOOP: MOV A,M STAX D INX H INX D DCR C JNZ LOOP HLT

(g) Software vs Hardware Interrupts

(h) Addressing Modes of 8085

Immediate: MVI A, 55H

Register: MOV A, B

Direct: LDA 2500H

Indirect: MOV A, M

Implied: CMA

SECTION – C (2 × 15 = 30 Marks)

Analytical and detailed system-level questions.

Q3. 8086 Microprocessor Features & Architecture

Features: 16-bit processor, 20-bit address bus (1 MB memory), 14 registers, pipelined architecture.

Architecture: Divided into:

Bus Interface Unit (BIU): Fetches instructions, manages queue, handles segment registers.

Execution Unit (EU): Executes instructions, performs ALU operations.

Q4. 8251 USART (Serial Communication)

Converts parallel → serial & serial → parallel data.

Functional Blocks: Data Bus Buffer, Transmitter, Receiver, Modem Control, and Control Word Register.

Interfacing: Connects to 8086 through RD’, WR’, CS’, and address lines.

Used in serial devices (modems, RS-232).

Q5. 8257 DMA Controller

Direct Memory Access (DMA) allows peripheral to transfer data directly to memory.

Blocks: Data Bus Buffer, Read/Write Control Logic, Priority Resolver, and DMA Channels (0–3).

Working: CPU sends HOLD → DMA takes control → transfers → sends HLDA (acknowledge).

Summary

The EEC406 – Introduction to Microprocessor exam thoroughly evaluates:

8085/8086 architecture & operations

Instruction set and addressing modes

Peripheral interfacing (8251, 8254, 8255, 8257)

Programming (assembly-level logic)

Interrupt handling and bus systems