THEORY EXAMINATION (SEM–IV) 2016-17 MICROPROCESSOR

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Course: B.Tech (Electrical / Electronics Engineering)
Subject Code: EE402
Subject Title: Microprocessor
Exam Type: Theory
Duration: 3 Hours
Maximum Marks: 100

SECTION – A (10 × 2 = 20 Marks)

Short conceptual questions testing basics of 8085 and 8086

No.	Question	Explanation
(a)	What is a Microprocessor?	CPU on a single IC performing ALU, control, and data operations. • 8085 operates at 5V supply and clock frequency = 3 MHz (typical).
(b)	Functions of Accumulator	Stores arithmetic and logical results; central register for data manipulation.
(c)	Define Subroutine	A reusable block of instructions executed when called by CALL, returned by RET.
(d)	IO/M’ Signal (8085)	Differentiates I/O and memory operations: IO/M’=0 → memory, IO/M’=1 → I/O.
(e)	Memory Chip Calculation	Memory needed = 128 KB = 131,072 bytes. Chip size = 2048 × 1 = 2048 bits = 256 bytes. → 131,072 / 256 = 512 chips required.
(f)	Define Interfacing	Process of connecting microprocessor to peripherals or memory ensuring proper signal communication.
(g)	CALL & RET	CALL saves return address to stack and jumps to subroutine; RET retrieves it and resumes program.
(h)	Segment Registers in 8086	CS, DS, SS, ES – divide memory (1MB) into 64KB segments for modular access.
(i)	Pipelining	Technique allowing simultaneous fetch and execution of instructions to increase throughput.
(j)	Instruction Queue in 8086	Prefetches up to 6 bytes in queue for faster execution via overlapping fetch and decode stages.

SECTION – B (5 × 10 = 50 Marks)

Descriptive questions combining theory, diagrams, and assembly programming

(a) Timing Diagram – Memory Write Cycle

Sequence: Opcode Fetch → Address on bus → Data transfer → Write enable.

Control Signals: ALE, WR’, IO/M’, READY, S0/S1.

Used to show synchronization between control, address, and data lines.

(b) 8255 Programmable Peripheral Interface (PPI)

Ports: A, B, C (8-bit each).

Groups: Group A (Port A + upper C), Group B (Port B + lower C).

Modes:

Mode 0 – Simple I/O

Mode 1 – Strobed I/O

Mode 2 – Bidirectional I/O

Used for keyboard, display, ADC/DAC interfacing.

(c) 8086 Architecture

Divided into Bus Interface Unit (BIU) and Execution Unit (EU).

BIU: Handles instruction fetch, queue, memory addressing.

EU: Executes instructions using ALU, registers, and control logic.

Memory addressing: 20-bit → 1 MB memory access.

(d) Addressing Modes of 8086

Immediate: MOV AX, 05H

Register: MOV BX, AX

Direct: MOV AX, [2000H]

Register Indirect: MOV AX, [BX]

Indexed/Base-Indexed: MOV AX, [BX+SI]

(e) Addressing Modes of 8085

Immediate → MVI A, 55H

Direct → LDA 2050H

Indirect → MOV A, M

Implied → CMA

(f) 8085 Architecture

Components: ALU, registers (A, B, C, D, E, H, L), accumulator, program counter, stack pointer, and flag register.

Control signals: RD’, WR’, ALE, IO/M’.

Clock frequency: 3 MHz typical; single +5V supply.

(g) Assembly Program – Division

Write a program to divide a 16-bit number by 8-bit number:

Load dividend (16-bit) into DE.

Load divisor into C.

Use subtraction or repeated division logic.

Store quotient and remainder in memory.

(h) Short Notes

Assembler-Level Program (ASM): Converts mnemonics into machine code.

Memory Space: Allocation of program and data memory in microprocessor address map.

SECTION – C (2 × 15 = 30 Marks)

In-depth analytical and programming questions

Q3. Programmable Timer/Counter (8254/8253)

Features: 3 independent 16-bit counters, 6 modes of operation.

Modes:

Interrupt on terminal count

One-shot

Rate generator

Square wave generator

Software triggered strobe

Hardware triggered strobe

Used in real-time systems for clock generation, frequency division, and pulse control.

Q4. DMA Controller (8237)

Purpose: Transfers data directly between memory and I/O without CPU involvement.

Blocks: Address register, count register, control logic, and DMA channels (0–3).

Operating Modes:

Demand Mode

Single Transfer Mode

Block Transfer Mode

Cascade Mode

Improves system performance by freeing CPU during large data transfers.

Q5. Assembly Program – Counting 0–9

Objective: Count 0 to 9 with a 1-second delay and repeat.

Logic:

Initialize accumulator and counter to 0.

Output count to a port (e.g., Port A).

Generate 1-second delay using HL pair loop (1 MHz clock).

Increment count; reset after 9.

Hint: Delay loop:

1 MHz clock → 1 μs per cycle → design loop ≈ 10⁶ cycles.\text{1 MHz clock → 1 μs per cycle → design loop ≈ 10⁶ cycles.}1 MHz clock → 1 μs per cycle → design loop ≈ 10⁶ cycles.