(SEM V) THEORY EXAMINATION 2024-25 INTEGRATED CIRCUITS

Subject Code: BEC501
Maximum Marks: 70
Time: 3 Hours
Paper ID: 310132

Question Paper Overview

SECTION A (2 × 7 = 14 Marks)

(Answer all questions briefly — conceptual and diagram-based)

a. Write the limitations of integrated circuits.
b. Draw a non-inverting amplifier with a voltage gain of 5.
c. State the applications of voltage-to-current (V–I) and current-to-voltage (I–V) converters.
d. Define a notch filter.
e. List the applications of sample and hold circuits.
f. Explain CMOS circuit logic.
g. Define lock-in range and capture range of a Phase Locked Loop (PLL).

SECTION B (Attempt any three × 7 = 21 Marks)

a. Calculate the overall voltage gain provided by IC 741 after drawing the small signal model of each stage.
b. Derive the expression for voltage gain in the KHN Biquad Filter. Draw the KHN filter circuit and derive transfer functions for both Band Pass (BPF) and Low Pass (LPF) filters.
c. Explain the methods of frequency compensation used in operational amplifiers.
d. Sketch the CMOS logic implementation of the given Boolean expression:

Y=(A+B‾)C+DE‾‾Y = \overline{(\overline{A + B})C + \overline{DE}}Y=(A+B​)C+DE​

e. Draw and explain the op-amp-based Voltage Controlled Oscillator (VCO) circuit.

SECTION C (Attempt one part from each question × 7 = 35 Marks)

Q3

(a) Explain how short-circuit protection is achieved in the output stage of an IC 741 op-amp. Also, draw and explain its frequency response.
OR
(b) Explain Wilson Current Mirror and Widlar Current Source with circuit diagrams and discuss advantages of Widlar source.

Q4

(a) Explain the principle of the Instrumentation Amplifier and derive its gain equation. Also, mention its applications.
OR
(b) Explain the operation of a triangular wave generator and sketch the capacitor and output voltage waveforms.

Q5

(a) Explain the methods of frequency compensation used in operational amplifiers.
OR
(b) Derive expressions for logarithmic and anti-logarithmic amplifiers with diagrams.

Q6

(a) Sketch the CMOS implementation of a J-K flip-flop and explain its operation. Also, discuss its limitations.
OR
(b) Realize the following 2-input logic gates using CMOS logic:
i. NAND
ii. EX-OR
iii. NOR

Q7

(a)
i. Draw the circuit of a monostable multivibrator using IC 555 timer.
ii. Design an astable multivibrator using IC 555 to generate a 2 kHz output with 75% duty cycle (given: C = 0.1 µF).
OR
(b) Explain, with a schematic, how a PLL can be used as:
i. Frequency Multiplier
ii. Frequency Translator

Key Topics for Revision

1. Limitations of Integrated Circuits

Power handling capability is low.

High voltage operation not feasible.

Difficult to repair individual components.

Limited passive components (inductors are hard to integrate).

2. Non-Inverting Amplifier (Gain = 5)

Av=1+RfR1=5⇒RfR1=4A_v = 1 + \frac{R_f}{R_1} = 5 \Rightarrow \frac{R_f}{R_1} = 4Av​=1+R1​Rf​​=5⇒R1​Rf​​=4

Circuit: Op-amp with input connected to non-inverting terminal, feedback resistor RfR_fRf​ and resistor R1R_1R1​ from output to ground.

3. V–I and I–V Converter Applications

V–I Converter: Used in analog current sources, transconductance amplifiers.

I–V Converter: Used in photo detectors, transimpedance amplifiers.

4. Notch Filter

Rejects a specific frequency (also called band-stop filter).

Used for hum elimination (50/60 Hz) in biomedical or audio systems.

5. Sample and Hold Circuit

Captures and holds analog voltage for ADCs.

Applications: Data acquisition, signal reconstruction, multiplexed systems.

6. CMOS Circuit Logic

Combines PMOS pull-up and NMOS pull-down transistors.

Offers low static power, high noise margin, and scalability.

Used in logic gates, flip-flops, memory cells.

7. PLL Ranges

Lock-in Range: Range within which PLL maintains lock after achieving synchronization.

Capture Range: Range within which PLL can initially acquire lock.

8. IC 741 Internal Structure

Stages: Differential input → Gain stage → Output buffer.

Frequency response: Single dominant pole, unity-gain bandwidth ≈ 1 MHz.

9. KHN Biquad Filter

Realizes LPF, HPF, and BPF using op-amps.

Key property: Simultaneous generation of multiple filter responses from one circuit.

Applications: Audio equalizers, signal analyzers.

10. Frequency Compensation Techniques

Miller Compensation: Dominant pole shifting using capacitor.

Pole Splitting: Separates poles to enhance phase margin.

Lead Compensation: Introduces a zero to stabilize high-frequency gain.

11. Wilson & Widlar Current Sources

12. Instrumentation Amplifier

Av=(1+2R1RG)R3R2A_v = \left(1 + \frac{2R_1}{R_G}\right)\frac{R_3}{R_2}Av​=(1+RG​2R1​​)R2​R3​​

High input impedance, excellent CMRR, differential amplification.

Used in sensors, medical instruments, strain gauges.

13. Log & Anti-Log Amplifiers

Based on the exponential I−VI-VI−V characteristic of diodes or BJTs.

Log Amplifier: Vo=−VTln⁡(IiIs)V_o = -V_T \ln \left(\frac{I_i}{I_s}\right)Vo​=−VT​ln(Is​Ii​​)

Anti-log Amplifier: Vo=−VTe(−Vi/VT)V_o = -V_T e^{(-V_i/V_T)}Vo​=−VT​e(−Vi​/VT​)

14. CMOS J-K Flip-Flop

Sequential logic element built from CMOS NAND/NOR gates.

Limitations: Race-around condition, timing constraints, higher transistor count.

15. 555 Timer Applications

Monostable Mode: Single pulse generation on trigger.

Astable Mode: Continuous square wave output.

• f=1.44(RA+2RB)Cf = \frac{1.44}{(R_A + 2R_B)C}f=(RA​+2RB​)C1.44​ D=RA+RBRA+2RB=0.75D = \frac{R_A + R_B}{R_A + 2R_B} = 0.75D=RA​+2RB​RA​+RB​​=0.75

(For f=2 kHz,C=0.1μFf = 2 \text{ kHz}, C = 0.1 \mu Ff=2 kHz,C=0.1μF)

16. PLL as Frequency Multiplier and Translator

Multiplier: PLL output frequency fo=N×fif_o = N \times f_ifo​=N×fi​.

Translator: Converts one frequency band to another by adjusting VCO frequency.

Exam Preparation Tips

Practice IC 741 circuit diagrams (small signal, compensation, response).

Revise 555 timer equations and PLL applications.

Prepare truth tables and CMOS implementations for logic gates.

Understand frequency compensation and op-amp frequency response.

Use clear labeled diagrams for instrumentation amplifiers, filters, and oscillators.