(SEM V) THEORY EXAMINATION 2023-24 MICROPROCESSOR & MICROCONTROLLER

This subject introduces the architecture, programming, and interfacing of Microprocessors (8085, 8086) and Microcontrollers (8051) — the foundational computing components of all embedded systems.

It combines hardware-level understanding (pins, buses, timing diagrams) with software-level programming (assembly language, addressing modes, and interrupts).
You’ll also learn how to interface peripherals like LCDs, ROM, RAM, and ADCs using these processors and controllers.

Exam Paper Overview

Instruction: Attempt all sections. If any data is missing, choose suitable values

Paper Pattern

SECTION A – Short Answer Questions (10 × 2 = 20 Marks)

These test fundamental concepts and definitions.

 Tip: Each answer should be short (2–3 lines) with an example (like “8085 uses RST for interrupt pins”).

SECTION B – Descriptive Questions (Any 3 × 10 = 30 Marks)

These are diagram-based and theory explanation type questions.

Q2(a) — Timing and Control Unit of 8085

Draw a detailed block diagram showing CLK generator, instruction register, timing signals (ALE, IO/M̅, RD̅, WR̅).

Explain how control signals synchronize data flow and memory/I/O access.

Q2(b) — Jump Instructions in 8085

Types: Unconditional (JMP) and Conditional (JZ, JNZ, JC, JNC, JP, JM, JPE, JPO).

Explain flag-based branching and address execution mechanism.

Q2(c) — Addressing Modes of 8086

Immediate, Register, Direct, Register Indirect, Indexed, Based, and Relative addressing modes.

Give examples:          MOV AX, BX → Register            MOV AX, [SI] → Register Indirect

MOV AX, [1234H] → Direct

Q2(d) — Memory Organization in 8051

8051 has 64 KB external code memory, 64 KB external data memory, 128 B internal RAM, 4 KB internal ROM.

Diagram showing division:            00H–7FH: Internal RAM            80H–FFH: SFR area

Bit-addressable area: 20H–2FH

Q2(e) — LCD Interfacing with 8051

Explain data pins D0–D7, control pins RS, RW, EN.

Connection through Port 2 or Port 1.

Steps: Initialize LCD → Send Commands → Display Data.

SECTION C – Analytical / Long Answer Questions (5 × 10 = 50 Marks)

Each question has two parts (choose one). They test application, interfacing, and programming.

Q3(a) — Interface 4 KB ROM + 16 KB RAM with 8085

Draw full address decoding using 74LS138 decoder.

Memory map:                      ROM: 0000H–0FFFH                   RAM: 4000H–7FFFH

Explain control signals: RD̅, WR̅, IO/M̅.

Q3(b) — Timing Diagram of MVI B, 20H

Opcode Fetch, Memory Read cycles.        Show T-states (T1–T3) and control signals (ALE, RD̅, WR̅).

Explain how data (20H) is transferred to register B.

Q4(a) — 8085 Instructions: LXI, XCHG, DAD, CMP, RAR

Define function and addressing modes:

LXI (Immediate), XCHG (Register Pair), DAD (Register Pair), CMP (Immediate/Register), RAR (Accumulator rotation).

Q4(b) — Interrupts in 8085

Types: Hardware (TRAP, RST7.5, RST6.5, RST5.5, INTR) and Software (RST n).

Explain priority, masking, vector locations, and enabling/disabling through SIM/RIM instructions.

Q5(a) — 8086 Maximum and Minimum Modes

Maximum Mode: For multiprocessor system; controlled by 8288 Bus Controller.

Minimum Mode: Single processor configuration.

Define Pin 24–31 functions for both modes (HOLD, HLDA, M/IO̅, WR̅, RD̅, DEN̅, DT̅/R̅).

Q5(b) — 8259 PIC Initialization (ICW1 & ICW2)

Draw flowchart for initialization.                      ICW1 defines interrupt mode (edge/level).

ICW2 defines interrupt vector base address.

Q6(a) — SFRs (Special Function Registers) of 8051

Examples:

ACC (E0H), B (F0H), PSW (D0H), SP (81H), DPL/DPH (82H/83H), P0–P3 (80H–B0H), TMOD/TCON (89H/88H).

Mention functions of each with addresses.

Q6(b) — Ports and Functions in 8051

P0: Dual function (I/O + address/data bus).                      P1: Simple I/O port.

P2: High byte of address bus.                  P3: Special functions (INT0, INT1, T0, T1, RXD, TXD, WR̅, RD̅).

Q7(a) — Timer Circuit in 8051

8051 has two 16-bit timers: Timer 0 & Timer 1.

Controlled by TMOD, TCON, THx/TLx registers.

Explain modes: Mode 0 (13-bit), Mode 1 (16-bit), Mode 2 (8-bit auto-reload).

Q7(b) — Addressing Modes in 8051

Immediate, Direct, Register, Register Indirect, Indexed, Bit-addressable.

Example:

MOV A, #25H → Immediate                MOV A, 40H → Direct        MOV A, @R0 → Register Indirect

Key Concepts to Revise

8085 Architecture: Registers, buses, and timing.

Addressing Modes & Instruction Set of 8085/8086.        Interrupt System and Vector Table.

Memory Interfacing & Address Decoding.                       8051 Architecture, SFRs, and Ports.

Timers, Counters, and Serial Communication in 8051.    Peripheral Interfacing (LCD, ADC, Keypad, etc.).

Conclusion
 

The KEC502 — Microprocessor & Microcontroller exam paper balances theory and practical circuit analysis.

It checks understanding from basic 8085 instruction timing to complex 8051 interfacing.

To score high:
 

Draw neat diagrams (architecture, memory maps, timing charts).

Write assembly code snippets where possible.
 

Highlight control signals and register names clearly.