(SEM V) THEORY EXAMINATION 2022-23 COMPUTER ARCHITECTURE AND ORGANIZATION

Course: B.Tech (Semester V)                                                                        Subject Code: KEC-051

Subject Name: Computer Architecture and Organization                         Time: 3 Hours

Total Marks: 100                                                                                         Note: Attempt all sections.

Section A – Short Answer Questions (2 × 10 = 20 Marks)

Answer all questions briefly:

Explain the Design Methodology.                                                           Describe a Stack Pointer.

What are Programmable Logic Devices (PLDs)?                                    Define Control Word.

Define Normalization in IEEE floating-point representation.                   What is a Coprocessor?

Differentiate between Horizontal and Vertical Organization.                What is Multiprogramming?

Define VHDL and mention its applications.

Differentiate between Program and Software.

Section B – Descriptive Questions (10 × 3 = 30 Marks)

Attempt any three:

Explain components at the processor design level and discuss design issues.

Describe CPU behavior using a flowchart and draw a block diagram of processor-memory communication with and without cache.

Design a 4-bit carry look-ahead adder and explain its working.

Write a short note on Virtual Memory and 2½ D Memory Organization.

Draw and explain a simple queuing model of a computer system.

Section C – Long Answer Questions (10 × 5 = 50 Marks)

Q3

(a) Explain the concept of Stack Organization.
or
(b) Represent the floating-point number 1.00010100 × 2⁻¹⁰ in IEEE format.

Q4

(a) Explain structure and behavior of a system. Write behavioral VHDL description of a Half Adder.
or
(b) What is Nano Programming? Explain the Control Unit with a block diagram.

Q5

(a) Differentiate between Hardwired Control and Microprogrammed Control, explaining both in detail.
or
(b) Write a program to evaluate X = (A + B) × (C × D) using an Accumulator-type computer with two-address instructions.

Q6

(a) Explain Booth’s Algorithm for signed multiplication and perform multiplication of (+14) × (–5) using Booth’s method.
or
(b) Explain the Daisy Chaining mechanism for bus arbitration and analyze Daisy chaining, Parallel, and Independent Requesting methods in terms of communication reliability.

Q7

(a) Explain how negative numbers are represented using 1’s complement and 2’s complement, along with their advantages and disadvantages.
or
(b) Write short notes on:                                 Data Processing and Data Movement

Encoder and Decoder                                     RISC and CISC

Virtual Address vs Physical Address                Multiplexer and De-Multiplexer