SECTION A (2 × 10 = 20 Marks)
Attempt all questions in brief
(a) Moore’s Law
Moore’s law states that the number of transistors that can be integrated on a single chip doubles approximately every eighteen to twenty-four months. This trend leads to continuous improvement in processing speed, functionality, and reduction in cost per transistor in VLSI technology.
(b) Defects in crystal structure
Two major defects that appear in crystal structures are point defects and line defects. Point defects include vacancies and interstitials, while line defects are mainly dislocations. These defects affect electrical and mechanical properties of semiconductor materials.
(c) Epitaxy
Epitaxy is a process in which a thin crystalline layer is grown on a crystalline substrate in such a way that the deposited layer follows the crystal orientation of the substrate. It is widely used in IC fabrication to obtain high-quality semiconductor layers.
(d) Auto doping
Auto doping is an unintentional doping process in which impurities from the substrate diffuse into the epitaxial layer during high-temperature processing. This can affect the electrical characteristics of devices if not properly controlled.
(e) Photoresist materials
Photoresist materials are light-sensitive organic polymers used in lithography. When exposed to ultraviolet light, their chemical structure changes, allowing selective removal during development to transfer circuit patterns onto wafers.
(f) Photo masking technique
The most commonly used photo masking technique in VLSI is optical photolithography. It uses ultraviolet light and a photomask to define circuit patterns on the wafer surface.
(g) Importance of diffusion furnace
A diffusion furnace provides a controlled high-temperature environment required for dopant diffusion into silicon wafers. It ensures uniform temperature distribution, controlled atmosphere, and precise dopant concentration.
(h) Gaseous source used in diffusion
Common gaseous sources used in diffusion include boron tribromide for p-type diffusion and phosphine or arsenic compounds for n-type diffusion.
(i) Sputtering
Sputtering is a physical vapor deposition process in which atoms are ejected from a target material due to bombardment by high-energy ions and deposited onto a substrate to form thin films.
(j) Ohmic contact in VLSI
An ohmic contact is a metal-semiconductor junction that allows current to flow easily in both directions with negligible resistance. It is essential for proper functioning of IC interconnections.
SECTION B (10 × 3 = 30 Marks)
(a) Czochralski (CZ) crystal growth process
The CZ process is used to grow single-crystal silicon ingots. In this process, high-purity polycrystalline silicon is melted in a quartz crucible. A small seed crystal is dipped into the molten silicon and slowly pulled upward while rotating. The molten silicon solidifies on the seed crystal, forming a cylindrical single-crystal ingot. This method allows precise control over crystal diameter and doping concentration.
(b) Molecular Beam Epitaxy (MBE)
Molecular Beam Epitaxy is a highly controlled epitaxial growth technique carried out in ultra-high vacuum. Atomic or molecular beams of elements are directed toward a heated substrate where layer-by-layer growth occurs. MBE provides excellent control over thickness and composition, making it suitable for advanced VLSI and optoelectronic devices.
(c) Electron Beam Lithography
Electron Beam Lithography uses a focused beam of electrons to write patterns directly onto a resist-coated wafer. It offers very high resolution and is mainly used for research and mask fabrication. Although it is slow and expensive, it is essential for fabricating very small feature sizes.
(d) Ion implantation technique
Ion implantation is a doping process in which dopant ions are accelerated and implanted into the semiconductor substrate. The depth and concentration of dopants are controlled by ion energy and dose. This method provides precise control and uniform doping compared to diffusion.
(e) Packaging in VLSI
Packaging in VLSI involves enclosing the IC chip in a protective casing that provides electrical connections, mechanical support, and heat dissipation. Techniques include wire bonding, flip-chip bonding, and surface mount packaging to ensure reliability and performance.
SECTION C
Q3 (a) Wafer cleaning technology
Wafer cleaning is a critical step in VLSI fabrication to remove contaminants such as dust, organic residues, and metallic impurities. Common cleaning techniques include RCA cleaning, wet chemical cleaning, and dry cleaning. Proper wafer cleaning improves yield, device reliability, and performance.
Q4 (a) Vapor Phase Epitaxy (VPE)
Vapor Phase Epitaxy is a process in which epitaxial layers are grown by chemical reactions of gaseous compounds on a heated substrate. Silicon tetrachloride or silane is commonly used as a source gas. VPE offers good uniformity and is widely used in IC fabrication.
Q5 (a) Pattern transfer process
Pattern transfer involves transferring circuit patterns from a photomask to the wafer surface using photolithography. The steps include wafer preparation, photoresist coating, exposure, development, etching, and resist removal. This process defines the geometric structure of IC components.
Q6 (a) Diffusion equation and Fick’s law
Diffusion in semiconductors is governed by Fick’s laws. Fick’s first law relates diffusion flux to concentration gradient, while Fick’s second law describes how concentration changes with time. The depth of diffusion is controlled by temperature and time during the diffusion process.
Q7 (a) Metallization and DC sputtering
Metallization is the process of forming metal interconnections on ICs. Common problems include electromigration, poor adhesion, and step coverage. In DC sputtering, a metal target is bombarded with ions, causing metal atoms to deposit uniformly on the wafer surface. This method provides good film quality and adhesion.
