(SEM V) THEORY EXAMINATION 2019-20 COMPUTER ARCHITECTURE AND ORGANIZATION

COMPUTER ARCHITECTURE AND ORGANIZATION (REC-052)

B.Tech (SEM-V) – AKTU

SECTION A

(Attempt all questions – 2 × 7 = 14 marks)

Q1 (a) A digital computer has a common bus system for 16 registers of 32 bits each. What size of multiplexers is needed?

To select one out of 16 registers for the bus, a 16-to-1 multiplexer is required for each bit.
Since each register has 32 bits, 32 multiplexers of size 16×1 are needed to construct the common bus.

Q1 (b) What is cache memory?

Cache memory is a small, high-speed memory located between CPU and main memory. It stores frequently used instructions and data to reduce access time and improve overall system performance.

Q1 (c) What is instruction cycle?

The instruction cycle is the sequence of steps performed by the CPU to execute an instruction. It includes fetch, decode, execute, and store phases.

Q1 (d) Discuss floating point number representation.

Floating point representation expresses numbers in scientific notation using sign, exponent, and mantissa. It allows representation of very large and very small numbers with higher precision.

Q1 (e) Explain concept of memory transfer.

Memory transfer refers to the process of moving data between memory and CPU registers or I/O devices using read and write operations controlled by control signals.

Q1 (f) What is meant by synchronous and asynchronous communication?

In synchronous communication, data transfer is controlled by a common clock.
In asynchronous communication, data transfer occurs without a clock and uses handshaking signals.

Q1 (g) Describe magnetic disk.

A magnetic disk is a secondary storage device that stores data magnetically on rotating platters. Data is accessed using read/write heads and provides large storage capacity with moderate speed.

SECTION B

(Attempt any three – 7 × 3 = 21 marks)

Q2 (a) Memory organization using RAM and ROM chips (numerical explanation).

The system requires 2 KB RAM and 4 KB ROM. RAM chips are 256 × 8 and ROM chips are 1024 × 8.
To build 2 KB RAM, 8 RAM chips are required.
To build 4 KB ROM, 4 ROM chips are required.

Using memory-mapped I/O, higher-order address bits are used to select RAM, ROM, and interface registers. Address decoding logic ensures correct chip selection.

Q2 (b) Explain instruction cycle in detail.

Instruction cycle consists of fetch cycle where instruction is loaded from memory, decode cycle where instruction is interpreted, execute cycle where operation is performed, and interrupt cycle if required. This cycle repeats for each instruction.

Q2 (c) Explain different addressing modes.

Addressing modes define how operands are accessed. Common modes include immediate, direct, indirect, register, indexed, and relative addressing. These modes provide flexibility and efficiency in instruction execution.

SECTION C

(Attempt any two – one from each unit, 7 × 2 = 14 marks)

Q5 (b) What are various addressing modes? Explain any five.

Immediate addressing stores operand within instruction itself.
Direct addressing gives memory address of operand.
Indirect addressing uses a pointer to access operand.
Register addressing stores operand in CPU register.
Indexed addressing adds index register value to address for array handling.

Q6 (a) Explain General Register Organization with diagram explanation.

General Register Organization consists of a set of registers connected through a common bus system. Multiplexers select source registers and control logic manages data transfer. It improves execution speed by reducing memory access.

Q7 (b) Write short notes on:

(i) Isolated vs Memory-Mapped I/O
(ii) RISC Architecture**

Isolated I/O uses separate address space for I/O devices, while Memory-Mapped I/O uses same address space for memory and I/O.
RISC architecture uses simple instructions, fixed instruction length, and pipelining to achieve high performance.