(SEM 5) THEORY EXAMINATION 2017-18 INTEGRATED CIRCUITS

Integrated Circuits (NEC-501)

Section-Wise Important Questions & Study Notes

SECTION–A

(Attempt all | 2 × 10 = 20)
Focus on definitions, short justifications, and quick numericals. Keep answers 2–3 lines.

Closed-Loop Gain Dependence
With very large open-loop gain, the closed-loop gain depends on external components (feedback network), not the op-amp itself.

Matched Transistors
Transistors fabricated on the same chip with identical characteristics (β, VBE) for accuracy and temperature tracking.

Slew Rate
Maximum rate of change of op-amp output voltage (V/µs). It limits high-frequency large-signal performance.

Super Diode
An op-amp-based precision rectifier that overcomes diode drop, enabling accurate rectification of small signals.

Applications of Analog Multiplier
AM modulation, frequency doubling, phase detection, power measurement.

Frequency Response of Filter
Variation of gain with frequency showing passband, cutoff, and stopband characteristics.

Comparator vs Schmitt Trigger
Comparator switches at a single threshold; Schmitt trigger has hysteresis (two thresholds) for noise immunity.

Need of Voltage Limiter
Protects circuits from over-voltage; clamps output within safe limits.

8-bit DAC Numerical
Step = 20 mV. Input 10110111₂ = 183₁₀ → Output = 183 × 20 mV = 3.66 V.

CMOS Logic
Uses complementary NMOS/PMOS; offers low power, high noise margin, and high density.

SECTION–B

(Attempt any THREE | 10 × 3 = 30)
 Mix of theory, derivations, and circuits.

1. Current Mirrors (Wilson MOS)

Desirable traits: accuracy, high output resistance, low sensitivity.

Explain Wilson MOS current mirror, improvements (cascode).

2. KHN Biquad Filter                       Note tuning advantages.

Draw KHN circuit.                           Derive voltage gain and transfer functions for BPF & LPF.

3. CMOS Logic Features & AOI/OAI          Low power, high fan-out, noise immunity.

Realize AOI and OAI using complementary PDN/PUN networks.

4. Quadrant Operation & Gilbert Multiplier          Explain 1-, 2-, and 4-quadrant operations.

Draw and explain Gilbert cell.

5. Phase Locked Loop (PLL)                                          Block diagram: phase detector, LPF, VCO.

Define lock-in range, capture range, pull-in time.   Applications: FM demodulation, frequency synthesis.

SECTION–C

(Attempt any TWO parts of each question | 10 × 5 = 50)
Long answers, derivations, numericals, and designs.

Q3

(a) Complementary Push-Pull Output Stage (BJT): operation, crossover distortion.
(b) Small-signal model of 741 second stage.
(c) Current Mirror Numerical: compute Iref, Io, IC/IB/IE values (step-wise).

Q4

(a) Generalized Impedance Converter (GIC): derive Z, simulate an inductor.
(b) RC Phase Shift Oscillator: derive frequency condition.
(c) Active vs Passive Filters; Design 2nd-order LP Butterworth (fc = 1 kHz).

Q5

(a) CMOS SR Flip-Flop: implementation & working.
(b) Two CMOS realizations of XOR (dual PDN/PUN).
(c) D-Flip-Flop using NAND CMOS gates.

Q6

(a) Triangular Wave Generator; obtain square wave.
(b) Temperature-compensated Log Amplifier (two op-amps).
(c) Schmitt Trigger: operation & design (VUT=2V, VLT=−1V, ±Vsat).

Q7

(a) IC 555 block diagram & functions.
(b) Dual-Slope ADC: principle & advantages.
(c) 555 Astable Design: 2 kHz, 75% duty cycle (derive R, C).