THEORY EXAMINATION (SEM–VI) 2016-17 VLSI DESIGN

VLSI DESIGN (EEC027)

B.Tech – Semester VI
 

Time: 3 Hours | Max Marks: 100

SECTION – A (10 × 2 = 20 marks)

(Attempt all questions)

(a) Write the classification of all CMOS circuit types.

CMOS circuits are classified into static CMOS circuits, dynamic CMOS circuits, pass transistor logic, transmission gate logic, and pseudo-NMOS logic.

(b) Define LSI, MSI, VLSI, and ULSI on number of transistor basis.

MSI contains up to 10³ transistors, LSI contains up to 10⁴ transistors, VLSI contains more than 10⁵ transistors, and ULSI contains more than 10⁷ transistors.

(c) Define testing.

Testing is the process of verifying the correctness of a VLSI circuit by detecting faults after fabrication.

(d) What are the three main domains of design?

The three main domains of VLSI design are behavioral domain, structural domain, and physical domain.

(e) What is body effect?

Body effect is the variation of threshold voltage of a MOS transistor due to change in source-to-body voltage.

(f) What are the AD HOC testable design techniques?

Ad hoc techniques include partitioning, adding test points, simplifying logic, and avoiding redundant logic.

(g) What are the needs for low power VLSI chips?

Low power VLSI chips are needed to reduce heat dissipation, increase battery life, improve reliability, and support portable devices.

(h) Differentiate between static logic circuits and dynamic logic circuits.

Static logic circuits store data indefinitely as long as power is supplied, while dynamic logic circuits store data temporarily using capacitors.

(i) Define interconnection.

Interconnection refers to the conductive paths that connect different components and circuits on a VLSI chip.

(j) Why does scaling have great importance in VLSI circuits?

Scaling increases speed, reduces power consumption, increases packing density, and lowers cost per function.

SECTION – B (5 × 10 = 50 marks)

(Attempt any five questions)

2(a) Draw CMOS inverter and explain transfer characteristics. Compare with resistive load inverter.

A CMOS inverter consists of a PMOS transistor connected to VDD and an NMOS transistor connected to ground.

Transfer Characteristics:
When input is low, PMOS conducts and output is high. When input is high, NMOS conducts and output is low.

Difference from resistive load inverter:
CMOS inverter has low power dissipation, higher noise margin, and better switching speed compared to resistive load inverter.

2(b) Explain read/write operation of SRAM memory cell.

An SRAM cell consists of six transistors.
During write operation, bit lines force data into the cell.
During read operation, stored data influences bit line voltage which is sensed by sense amplifiers.

2(c) Explain construction and operation of n-channel depletion MOS transistor.

A depletion type MOS transistor has a pre-formed channel.
It conducts even at zero gate voltage and requires negative gate voltage to turn off.

The V–I characteristics show current flow even when VGS = 0.

2(d) What are FPGAs? Discuss salient features.

Field Programmable Gate Arrays are programmable logic devices.

Features include reconfigurability, fast prototyping, parallel processing, high flexibility, and shorter development time.

2(e) Explain polysilicon gate self-aligned NMOS fabrication process.

This process uses polysilicon gate as a mask for source and drain diffusion, ensuring precise alignment and improved performance.

2(f) Explain issues involved in BIST testing.

Issues include area overhead, performance degradation, test complexity, and fault coverage limitations.

2(g) Describe stick layout design style for CMOS circuit design.

Stick diagrams represent simplified layouts using colored lines to indicate different layers, helping in planning chip layout.

2(h) Define transconductance and output conductance. Derive expression for transconductance.

Transconductance is the rate of change of drain current with gate voltage.
gm = ∂ID / ∂VGS

For MOS transistor,
gm = 2ID / (VGS − VT)

SECTION – C (2 × 15 = 30 marks)

(Attempt any two questions)

3. Types of faults in logic circuits and testing for stuck-at fault.

Common faults include stuck-at faults, bridging faults, open faults, and delay faults.

Stuck-at fault assumes a node is permanently at logic 0 or 1.
Testing involves applying test vectors to detect incorrect output responses.

4. Explain combined voltage and dimension scaling model. Compare scaling parameters.

In combined scaling, both dimensions and voltage are scaled to reduce power.

5. Parameters of good VLSI design and cell-based design technique.

Important parameters include speed, power consumption, area, reliability, and testability.

Cell-based design:
Uses pre-designed standard cells which are interconnected to form a complete circuit.
It reduces design time and improves reliability.