(SEM VII) THEORY EXAMINATION 2021-22 VLSI DESIGN

VLSI DESIGN – KEC 072

B.Tech (Semester VII) – Detailed Answers

SECTION A – Descriptive Answers (2 Marks Each)

a) Photolithography

Photolithography is a microfabrication process used in IC manufacturing to transfer geometric patterns from a photomask onto a silicon wafer using light-sensitive material called photoresist. It plays a crucial role in defining circuit patterns during CMOS fabrication.

b) Need for Low Power VLSI Circuits

Low power VLSI circuits are essential due to increased device density, battery-operated portable systems, thermal constraints, reliability issues, and power-aware computing. Reducing power dissipation improves performance, battery life, and chip reliability.

c) Contamination Delay

Contamination delay is the minimum time after an input change before the output begins to change. It is important in timing analysis to avoid race conditions and ensure correct sequential circuit operation.

d) Logical Effort (with Example)

Logical effort is a measure of how much worse a logic gate is at driving current compared to an inverter.
Example: NAND gate has higher logical effort than an inverter due to stacked transistors, resulting in higher delay.

e) Static Power vs Dynamic Power

f) 2:1 MUX Using CMOS Transmission Gate

A 2:1 multiplexer using transmission gates employs complementary NMOS and PMOS switches controlled by select and its complement. This provides full voltage swing and low resistance for both logic levels.

g) Storage Elements

Storage elements store binary information and include latches, flip-flops, SRAM cells, and DRAM cells. They are used in registers, memories, and sequential circuits.

h) SRAM vs DRAM

i) Controllability and Observability

Controllability measures how easily a node can be set to logic 0 or 1.
Observability measures how easily a node’s value can be observed at output.
Both are crucial in VLSI testing.

j) Stuck-at-0 and Stuck-at-1 Faults

A stuck-at-0 fault forces a signal permanently to logic 0, while a stuck-at-1 fault forces it to logic 1. These are common fault models in digital circuit testing.

SECTION B – Long Answers (10 Marks Each)

2(a) Semiconductor Hierarchy, Moore’s Law & VLSI Testing

Hierarchy of Semiconductor Integration:

SSI (Small Scale Integration)                                          MSI (Medium Scale Integration)

LSI (Large Scale Integration)                                          VLSI (Very Large Scale Integration)

ULSI (Ultra Large Scale Integration)

Moore’s Law states that the number of transistors on a chip doubles approximately every 18–24 months, leading to increased performance and reduced cost per function.

VLSI Testing ensures correctness, reliability, and manufacturability of chips. It includes fault modeling, test pattern generation, BIST, and scan-based testing.

2(b) Elmore Delay Model

The Elmore delay model estimates delay in RC networks by approximating the first moment of impulse response.
For an RC tree, delay is calculated as the sum of resistance multiplied by downstream capacitances.

Merits:                                                               Simple and fast

Useful in early design stages                              Reasonably accurate for interconnect delay estimation

2(c) Domino CMOS vs NP Domino CMOS

Domino CMOS:                                                Uses dynamic precharge-evaluate logic

Faster than static CMOS                                    Suffers from monotonicity problem

NP Domino CMOS:                                         Uses both n-type and p-type dynamic logic

Allows both rising and falling transitions         Higher complexity but better performance

2(d) Read/Write Operation of SRAM Cell

An SRAM cell consists of six transistors (6T).

Write: Data is forced through bit lines

Read: Cell state is sensed without disturbing data

Multiple 1-bit cells are arranged in rows and columns with decoders and sense amplifiers to form larger memory arrays.

2(e) Issues in BIST Techniques

Issues include area overhead, power consumption, fault coverage limitations, test pattern quality, performance degradation, and increased design complexity.

SECTION C – Very Long Answers (10 Marks Each)

3(a) Y-Chart and VLSI Design Process

The Y-chart represents VLSI design at three abstraction levels:

Behavioral (what the system does)

Structural (how components are connected)

Physical (layout and fabrication)

Design proceeds through specification, architecture, logic design, circuit design, layout, fabrication, and testing.

Advantages:                                                           Structured design approach

Supports hierarchy and abstraction                        Improves design productivity

3(b) CMOS Fabrication Using n-Well Process

Steps include wafer preparation, oxidation, photolithography, n-well formation, gate oxide growth, polysilicon deposition, source/drain diffusion, metallization, and passivation.
(Neat labeled diagram to be drawn in exam)

4(a) Total Power Dissipation in CMOS

Total power:

Ptotal=Pdynamic+Pstatic+PshortP_{total} = P_{dynamic} + P_{static} + P_{short}Ptotal​=Pdynamic​+Pstatic​+Pshort​

Dynamic power:

P=αCLVdd2fP = \alpha C_L V_{dd}^2 fP=αCL​Vdd2​f

Static power is due to leakage currents, and short-circuit power occurs during switching when both NMOS and PMOS are ON.

4(b) RC Delay Model for Interconnects

Interconnects are modeled as distributed RC networks. Delay increases with wire length, resistance, and capacitance, making interconnect delay dominant in deep submicron technologies.

5(a) NORA and TSPC Dynamic CMOS Logic

NORA Logic: Combines dynamic logic blocks without inverters, improving speed.
TSPC Logic: Uses single-phase clocking, reducing clock complexity and power.

5(b) Pre-Charge Evaluate Logic & SRAM/DRAM Architecture

Precharge-evaluate logic precharges nodes and conditionally discharges them during evaluation.
SRAM uses bistable latches; DRAM uses capacitor-based storage.

6(a) DRAM Cell, Leakage and Refresh

DRAM stores charge on a capacitor which leaks over time. Periodic refresh is required to maintain data integrity.

6(b) Types of Power Dissipation in CMOS

Dynamic switching power

Short-circuit power

Leakage power (subthreshold, gate leakage)

7(a) Parallel Processing in Low Power CMOS

Parallel processing reduces operating frequency while maintaining throughput, leading to quadratic reduction in dynamic power.

7(b) Short Notes

i) Adiabatic Logic Circuits
These reduce energy loss by recycling charge during switching using time-varying power supplies.

ii) Scan Cell Based Approach
Scan cells convert sequential circuits into combinational ones for easier testing and higher fault coverage.