This document contains the complete B.Tech (Semester III) Theory Examination 2017–18 question paper for the subject Computer Organization & Architecture (RCS-302). The paper consists of 2 printed pages, carries 70 marks, and evaluates a student's understanding of computer hardware structure, processor operations, memory organization, arithmetic algorithms, and control unit design.
Section A — Short Conceptual Questions
Section A carries 14 marks and includes seven brief questions testing core theoretical concepts in computer architecture. Students are asked to:
Draw the D Flip-Flop circuit diagram
Differentiate between RAM and ROM
Write a short note on the pipelining process
Compare serial vs. parallel communication
Perform 2’s complement addition on signed numbers
Write speed-up performance laws
Differentiate between horizontal and vertical microprogramming
These questions verify the student's fundamental understanding of digital hardware and basic architecture concepts.
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Section B — Descriptive & Diagram-Based Questions
Section B (21 marks) requires students to attempt any three out of five questions. These questions demand deeper knowledge, diagram drawing, algorithm explanation, and architectural analysis:
Definition of Programmable Logic Devices (PLDs) and programming techniques
Block diagram of a small Accumulator-based CPU and explanation of IEEE 754 32-bit floating-point format
Data path for a sequential n-bit binary divider, along with non-restoring division algorithm and example
Structure, format, and organization of a microprogrammed control unit
Concept of locality of reference with examples
This section tests both theoretical knowledge and the ability to represent architectural concepts visually.
Section C — Long Analytical & Algorithmic Problems
Section C includes several 7-mark questions where students must attempt one part from each group. These are advanced, high-level computer architecture topics requiring explanation, algorithm derivation, and system analysis:
Topics include:
1. Processor Architecture
Difference between RISC and CISC processors
Detailed explanation of Booth’s multiplication algorithm
2. Arithmetic & Logic Unit (ALU) Operations
Data path of 2’s complement multiplier with Robertson algorithm
Sequential ALU design with diagrams
3. Memory Organization & DMA
Structure of an 8M × 8-bit DRAM chip
Working of DMA controller with diagrams
4. Control Unit Design & Pipelining
Hardwired control unit design methods with GCD processor example
Measurement of pipeline performance with a space–time diagram
5. Cache Mapping & Disk Performance
Types of cache address mapping
Calculation of average latency and data transfer rate for a disk with given hardware specifications
Summary
This exam paper provides a comprehensive assessment of student knowledge across:
Digital circuits
CPU architecture
Control unit design
Memory systems
Arithmetic algorithms
Pipelining techniques
Storage device performance
It integrates theoretical questions, algorithmic problems, numerical calculations, and hardware diagrams, making it a complete and valuable academic resource for students studying computer organization and architecture.
