(SEM V) THEORY EXAMINATION 2024-25 VLSI TECHNOLOGY

Subject Code: BEC054
Maximum Marks: 70
Time: 3 Hours
Paper ID: 310955

Question Paper Overview

SECTION A (2 × 7 = 14 Marks)

(Short and fundamental questions from semiconductor fabrication basics)

a. What is an ingot?
b. Differentiate between homo-epitaxy and hetero-epitaxy.
c. List the figures of merit in the photolithographic process.
d. Name the etchant commonly used to remove silicon.
e. Name any two solid sources for n-type dopant sources.
f. Write the advantage of using aluminum in metallization.
g. Define throughput for IC fabrication.

SECTION B (Attempt any three × 7 = 21 Marks)

a. Compare FZ (Float Zone) and CZ (Czochralski) techniques for crystal growth. Explain evaluation of crystal.
b. Explain the basic transport processes and reaction kinetics of Vapor Phase Epitaxy (VPE).
c. Define photolithography. Discuss the steps of mask generation with a diagram.
d. Explain models for diffusion in solids and describe Fick’s First Law of Diffusion.
e. Write short notes on:

(i) Sputtering          (ii) Applications of Metallization

SECTION C (Attempt one part from each question × 7 = 35 Marks)

Q3

(a) Explain the different steps involved in shaping of silicon wafers.
OR
(b) Why is oxidation necessary in IC fabrication? Compare high-pressure oxidation and plasma oxidation.

Q4

(a) Explain Molecular Beam Epitaxy (MBE) with a diagram. Discuss its advantages and disadvantages.
OR
(b) Write short notes on:

(i) Pre-oxidation cleaning          (ii) Wet oxidation

Q5

(a) Explain the deposition methods and deposition variables for silicon dioxide. Also explain the step coverage problem in SiO₂ deposition.
OR
(b) Write short notes on:

(i) Wet etching                   (ii) Projection printing

Q6

(a) Explain the ion implantation technique with a diagram of equipment. Discuss advantages and disadvantages of ion implantation.
OR
(b) Derive an expression for complementary error function (erfc) diffusion profile.

Q7

(a) Explain the CMOS fabrication process sequence using twin-well technology, with diagrams.
OR
(b) Discuss the need for packaging in VLSI and elaborate on packaging design considerations.

Key Topics for Revision

1. Crystal Growth Techniques

2. Epitaxy

Homo-epitaxy: Grown layer of same material (e.g., Si on Si).

Hetero-epitaxy: Grown layer on different material (e.g., GaAs on Si).

Molecular Beam Epitaxy (MBE):            Ultrahigh vacuum system.

Precise atomic control.                             Used in high-speed and optoelectronic devices.

Advantages: Uniform, controlled growth.     Disadvantages: Expensive, low throughput.

3. Photolithography

Steps:

Substrate preparation.                       Photoresist coating.

Soft baking.                                       Mask alignment and exposure.

Development.                                   Hard baking.

Etching.                                             Stripping.

Figures of Merit: Resolution, sensitivity, contrast, and throughput.

4. Diffusion Process

Describes movement of dopant atoms in silicon.

Fick’s First Law:

• J=−DdCdxJ = -D \frac{dC}{dx}J=−DdxdC​

where J = flux, D = diffusion coefficient, C = concentration.

Complementary Error Function (erfc) Profile:

• C(x,t)=Cs erfc(x2Dt)C(x,t) = C_s \, \text{erfc}\left(\frac{x}{2\sqrt{Dt}}\right)C(x,t)=Cs​erfc(2Dt​x​)

5. Oxidation in IC Fabrication

Purpose: Creates SiO₂ insulating layer for masking and passivation.

High-Pressure Oxidation: Faster growth rate, uniform.

Plasma Oxidation: Low temperature, suitable for shallow oxides.

6. Deposition Techniques

7. Etching

Wet Etching: Uses chemicals (HF, HNO₃). Isotropic and simple.

Dry Etching: Plasma-based, anisotropic, higher precision.

Projection Printing: Optical projection for pattern transfer (used in photolithography).

8. Ion Implantation

Principle: High-energy ions implanted into silicon substrate.

Advantages: Precise control, room-temperature process.

Disadvantages: Lattice damage, requires annealing.

Equipment: Ion source → accelerator → mass analyzer → target chamber.

9. CMOS Twin-Well Fabrication

Combines n-well and p-well processes.

Steps: Oxidation → Photolithography → Well implantation → Gate oxide → Polysilicon gate → Source/Drain formation → Metallization → Passivation.

Advantages: Balanced threshold voltages, latch-up prevention.

10. Metallization & Packaging

Aluminum: Preferred for its low resistivity and good adhesion.

Sputtering: Used to deposit thin metal films.

Packaging: Protects IC, provides electrical connections, aids heat dissipation.

Design Considerations: Electrical performance, mechanical strength, thermal management, cost.

11. Throughput in Fabrication

Definition: Number of wafers processed per unit time.

Depends on process speed, automation, and yield.

Exam Preparation Tips

Memorize key process diagrams: MBE, ion implantation, CMOS fabrication.

Revise mathematical expressions: Diffusion laws, erfc profile.

Focus on comparisons: FZ vs CZ, oxidation types, epitaxy methods.

Write short, neat notes for Section A; detailed flowcharts and labeled diagrams for Sections B & C.