(SEM V) THEORY EXAMINATION 2023-24 COMPUTER ARCHITECTURE AND ORGANIZATION

Course: B.Tech (Semester V)

Subject Code: KEC051

Subject: Computer Architecture and Organization

Maximum Marks: 100

Time: 3 Hours

Pattern:

Section A: 10 short answer questions × 2 marks = 20

Section B: Attempt any 3 × 10 marks = 30

Section C (Q3–Q7): Attempt one part from each = 50

SECTION A – Short Answer Questions (2 × 10 = 20 Marks)

a. Compare Combinational and Sequential Logic Circuits.
b. Explain the use of Program Counter (PC).
c. Compare PLA (Programmable Logic Array) and PAL (Programmable Array Logic).
d. Describe Moore’s Law.
e. Write the differences between EPROM, EEPROM, and Flash Memory.
f. Represent (–320) in 16-bit binary sign magnitude and two’s complement form.
g. Describe Floating Point Number Representation with an example.
h. Compare Combinational and Sequential Logic Circuits (repeated).
i. Differentiate between Cache Memory and RAM.
j. Compare SRAM and DRAM.

SECTION B – Analytical / Conceptual Questions (Any 3 × 10 = 30 Marks)

a. Explain in detail:
i. Encoder and Decoder
ii. Virtual Address and Physical Address

b. Draw and explain CPU Instruction Cycle with Interrupts.

c. Show the multiplication process using Booth’s Algorithm for binary numbers (+12) × (–16).

d. Discuss different Pipeline Hazards in detail.

e. Discuss various Types of Secondary Memories.

SECTION C – Long / Descriptive Questions (Each 10 Marks)

Q3. Addressing and Interrupts

a. What is Addressing Mode? Explain any five types with examples.
b. Define the two approaches to handle multiple interrupts and write their disadvantages.

Q4. Arithmetic and IAS Structure

a. Find (28 – 45) using 8-bit Two’s Complement Arithmetic. Show steps, decimal result, and explain why it’s better.
b. Draw and explain the Expanded Structure of IAS Computer and its components.

Q5. Memory Systems

a. Define the seven RAID levels. How is redundancy achieved in each?
b. Draw the DRAM Binary Cell Structure and explain how bits are read/written.

Q6. Processor and Bus Systems

a. Explain how processor performance can be improved by:

Increasing microprocessor speed,                        Balancing component performance,

Improving chip design.

b. Why are Multiple Buses used? Name common Multiple-Bus Hierarchies and explain one with a diagram.

Q7. Cache and Mapping

a. Name all elements essential for Cache Design. Discuss replacement algorithms (FIFO, LRU, Random).
b. What is a Mapping Function? Explain Direct Mapping with an example and differentiate it from Associative Mapping.