(SEM V) THEORY EXAMINATION 2021-22 MICROPROCESSORS AND MICROCONTROLLERS

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MICROPROCESSORS AND MICROCONTROLLERS (KEC-502)

B.Tech (Sem V) – Exam Notes & Solved Guide

SECTION A – Short Answer Type (2 Marks Each)

a. Specifications of 8085 Microprocessor
8085 is an 8-bit microprocessor with 16-bit address bus, 8-bit data bus, 64 KB memory addressing capacity, 3 MHz clock frequency, five hardware interrupts, and on-chip clock generator.

b. Disadvantages of Memory-Mapped I/O
Memory-mapped I/O reduces available memory space and requires more instructions compared to I/O-mapped I/O.

c. T-States Required

MVI A, 34H → 7 T-states LXI H, 2000H → 10 T-states

d. Interrupts of 8085

Maskable: RST 5.5, RST 6.5, RST 7.5 Non-Maskable: TRAP

Software Interrupts: RST 0 to RST 7

e. Physical, Segment & Offset Address (8086)
Physical address = Segment × 16 + Offset.
Segment address specifies memory segment base, offset gives location within segment.

f. Memory Segments in 8086
Code Segment, Data Segment, Stack Segment, Extra Segment.

g. Stack Organization in 8051
Stack is located in internal RAM and grows upward. Stack Pointer (SP) holds the top of stack address.

h. Bit-Addressable RAM in 8051
16 bytes (20H–2FH) of internal RAM are bit-addressable, allowing 128 individual bits.

i. PSW & TCON (8051)
PSW stores flags and register bank select bits.
TCON controls timers and external interrupts.

j. Instructions

MOV A,@R0 → Moves data pointed by R0 to accumulator

MOVX A,@DPTR → Transfers data from external memory to accumulator

SECTION B – Descriptive Answers (10 Marks Each)

a. Signals of 8085

HOLD: Requests CPU to release buses HLDA: Acknowledges HOLD

READY: Inserts wait states ALE: Latches address

CLK OUT: System clock output

b. Instruction Execution & Memory Occupied

LXI H,2000H: Loads HL pair → 3 bytes LDA 2000H: Loads A from memory → 3 bytes

RAL: Rotate accumulator left → 1 byte JNC: Jump if no carry → 3 bytes

MVI: Move immediate → 2 bytes

c. 8255 PPI – Control Word Register

CWR defines operating modes of ports A, B, and C.
BSR mode allows individual bit set/reset of Port C.

d. PSW of 8051

Contains Carry, Auxiliary Carry, Parity, Overflow flags, and register bank selection bits.

e. I/O Ports of 8051

Ports act as both input/output and alternate function pins (serial, timers, interrupts).

SECTION C – Long Answer / Programming

3(a) Interfacing EPROM & RAM with 8085

Using 3×8 decoder, address lines select EPROM (16 KB using two 8K×8) and RAM (8 KB using two 4K×8). Chip select is generated via decoder outputs.

3(b) Interfacing Input & Output Devices

Input uses IN instruction, output uses OUT instruction. Address decoding selects devices.

4(a) Program: Largest Number (2000H–200AH)

LXI H,2000H MOV A,M INX H MVI C,0AH LOOP: CMP M JNC SKIP MOV A,M SKIP: INX H DCR C JNZ LOOP STA 3000H HLT

Explanation: Compares numbers sequentially and stores the largest at 3000H.

4(b) Interrupt Priorities & SIM/RIM

Priority: TRAP → RST 7.5 → RST 6.5 → RST 5.5 → INTR.
SIM: Masks interrupts, controls serial output.
RIM: Reads interrupt status and serial input.